PXR40RM Datasheet, PDF (934/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
If the eSCI module is in LIN mode and the system stop signal is asserted while a LIN byte field or character
reception is running, the eSCI module aborts the reception immediatley. None of the receiver related
register flags will be set.
If the eSCI module is in LIN mode and the system stop signal is asserted and no transmission or reception
is running, the eSCI module resets the LIN protocol engine to its idle state, resets the write access counter
of the LIN Transmit Register (eSCI_LTR) and enters the Stop mode.
26.1.6.4.4 Leaving Stop Mode into LIN Mode
If the eSCI module is in Stop mode and the system stop signal is de-asserted and the LIN bit is set and the
MDIS bit is 0, the eSCI module will enter the LIN mode. The TXRDY flag will bet set. No data will be
transmitted as long as new LIN frame header data provided by the application. If the receiver is still
enabled, it starts the detection of the start bit.
26.2 External Signal Description
The eSCI module is connected two a total of two external pins.
26.2.1 Detailed Signal Descriptions
26.2.1.1 eSCI Transmit Pin (TXD)
This pin serves as transmit data output and as the receive data input of eSCI.
26.2.1.2 eSCI Receive Pin (RXD)
This pin serves as receive data input of the eSCI.
26.3 Memory Map and Register Definition
This section provides the memory map and a detailed description of the memory mapped registers.
26.3.1 Memory Map
Table 26-3 provides a 32-bit view of the eSCI’s memory map. This table gives the register offset w.r.t.
module base address eSCI_BASE.
Table 26-3. eSCI 32-bit Memory Map
Offset
Register
0x0000
Baud Rate Register (eSCI_BRR)
Control Register 1 (eSCI_CR1)
0x0004
Control Register 2 (eSCI_CR2)
SCI Data Register (ESCI_DR)
0x0008
Interrupt Flag and Status Register 1 (eSCI_IFSR1) Interrupt Flag and Status Register 2 (eSCI_IFSR2)
26-6
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor