PXR40RM Datasheet, PDF (833/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexCAN Module
24.3.4.6 Rx 15 Mask (FLEXCAN_x_RX15MASK)
This register is provided for legacy support. Setting the MBFEN bit in FLEXCAN_x_MCR causes the
FLEXCAN_x_RX15MASK Register to have no effect on the module operation.
When the MBFEN bit is negated, FLEXCAN_x_RX15MASK is used as acceptance mask for the
Identifier in Message Buffer 15. When the FEN bit in FLEXCAN_x_MCR is set (FIFO enabled), the
RXG14MASK also applies to element 7 of the ID filter table. This register has the same structure as the
Rx Global Mask Register. It must be programmed while the module is in Freeze Mode, and must not be
modified when the module is transmitting or receiving frames.
• Address Offset: 0x18
• Reset Value: 0xFFFF_FFFF
24.3.4.7 Error Counter Register (FLEXCAN_x_ECR)
This register has 2 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error Counter
(Tx_Err_Counter field) and Receive Error Counter (Rx_Err_Counter field). The rules for increasing and
decreasing these counters are described in the CAN protocol and are completely implemented in the
FlexCAN module. Both counters are read only except in Freeze Mode, where they can be written by the
CPU.
Writing to the Error Counter Register while in Freeze Mode is an indirect operation. The data is first
written to an auxiliary register and then an internal request/acknowledge procedure across clock domains
is executed. All this is transparent to the user, except for the fact that the data will take some time to be
actually written to the register. If desired, software can poll the register to discover when the data was
actually written.
FlexCAN responds to any bus state as described in the protocol, e.g. transmit ‘Error Active’ or ‘Error
Passive’ flag, delay its transmission start time (‘Error Passive’) and avoid any influence on the bus when
in ‘Bus Off’ state. The following are the basic rules for FlexCAN bus state transitions.
• If the value of Tx_Err_Counter or Rx_Err_Counter increases to be greater than or equal to 128, the
FLT_CONF field in the Error and Status Register is updated to reflect ‘Error Passive’ state.
• If the FlexCAN state is ‘Error Passive’, and either Tx_Err_Counter or Rx_Err_Counter decrements
to a value less than or equal to 127 while the other already satisfies this condition, the FLT_CONF
field in the Error and Status Register is updated to reflect ‘Error Active’ state.
• If the value of Tx_Err_Counter increases to be greater than 255, the FLT_CONF field in the Error
and Status Register is updated to reflect ‘Bus Off’ state, and an interrupt may be issued. The value
of Tx_Err_Counter is then reset to zero.
• If FlexCAN is in ‘Bus Off’ state, then Tx_Err_Counter is cascaded together with another internal
counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
Tx_Err_Counter is reset to zero and counts in a manner where the internal counter counts 11 such
bits and then wraps around while incrementing the Tx_Err_Counter. When Tx_Err_Counter
reaches the value of 128, the FLT_CONF field in the Error and Status Register is updated to be
‘Error Active’ and both error counters are reset to zero. At any instance of dominant bit following
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
24-23