PXR40RM Datasheet, PDF (901/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
the DSPI_COMPR is compared to. The MTRIG output signal is asserted every time a change in data is
detected.
25.4.4.5.3 Triggered Control
For Triggered Control initiation of a transfer is controlled by the Hardware Trigger signal (HT). The TPOL
bit in the DSPI_DSICR selects the active edge of HT. For HT to have any affect, the TRRE bit in the
DSPI_DSICR must be set.
25.4.4.5.4 Triggered or Change In Data Control
For Triggered or Change in Data Control initiation of a transfer is controlled by the HT signal or by the
detection of a change in data to be serialized.
25.4.4.6 Multiple Transfer Operation (MTO)
In DSI Configuration the MTO feature allows for multiple DSPIs within a device to be chained together
in a parallel or serial configuration. The parallel chaining allows multiple DSPIs internal to a device and
multiple SPI devices external to a device to share SCK and PCS signals thereby saving pins. The serial
chaining allows bits from multiple DSPIs to be concatenated into a single DSI frame. MTO is enabled by
setting the MTOE bit in the DSPI_DSICR.
In parallel and serial chaining there is one bus master and multiple bus slaves. The bus master initiates and
controls the transfers, but the DSPI slaves generate trigger signals for the bus DSPI master when an
internal condition in the slave warrants a transfer. The DSPI slaves also propagate triggers from other
slaves to the master. When a DSPI slave detects a trigger signal on its HT input, the slave generates a
trigger signal on the MTRIG output.
Serial and parallel chaining require multiplexing of signals external to the DSPI.
25.4.4.6.1
Parallel Chaining
NOTE
When using the DSPI in DSI mode, with MTO enabled, and clock phase set
to leading edge capture (DSPIx_CTARn[CPHA]=0) the first bit shifted out
of the master DSPI into the slave DSPI is read as “1”, regardless of the
actual value. To account for this behavior, the following options are
recommended:
• Select CPHA=1 (following edge capture), if suitable for external slave
devices.
• Set the first bit of the transferred data to “1”, or ignore the first bit.
• Externally connect master SOUT to SIN of the first slave, rather than
connecting via internal signals. This requires setting
SIU_DISR_SINSELx bits of the first slave DSPI to “00” and
configuring the first slave's SIN pin and master SOUT pin as DSPI SIN
and DSPI SOUT, respectively.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-41