PXR40RM Datasheet, PDF (1046/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Field
0
EOQ
1
PAUSE
2
REP
3–4
5
EB
6
BN
7
R/W
8–11
MESSAGE_
TAG
12–23
24–31
ADC_REG_
ADDRESS
End Of Queue Bit
Table 27-35. Field Descriptions
Description
Pause Bit
Repeat/loop Start Point Indication Bit
Reserved
Must be 0b0
Buffer Number Bit. Refer to Section , Conversion Command Format for the Standard Configuration.
Read/Write bit. An asserted R/W bit indicates a read configuration command.
0 Write1Read
MESSAGE_TAG Field. Refer to Section , Conversion Command Format for the Standard Configuration.
Reserved
ADC Register Address. The ADC_REG_ADDRESS field selects a register on the ADC register set to be
written or read. Only half-word addresses can be used.
ADC Result Format for On-Chip ADC Operation
When the FIFO Control Unit receives a return data message, it decodes the MESSAGE_TAG field and
stores the 16-bit data into the appropriate RFIFO. This section describes the ADC result portion of the
result message returned by the on-chip ADCs. The 16-bit data stored in the RFIFOs can be:
• Data read from an ADC register with a read configuration command. In this case, the stored 16-bit
data corresponds to the contents of the ADC register that was read.
• A time stamp. In this case, the stored 16-bit data is the value of the time base counter latched when
the EQADC detects the end of the analog input voltage sampling. For details see Section 27.7.6.3,
Time Stamp Feature.
• A conversion result, coming directly from the ADCs. In this case, the stored 16-bit data contains a
right justified 14-bit result data. The conversion result can be calibrated or not depending on the
status of CAL bit in the command that requested the conversion¹. When the CAL bit is negated,
this 14-bit data is obtained by executing a 2-bit left-shift on the 12-bit data resultant from the
resolution adjustment on the 8 or 10 or 12-bit data received from the ADC. The resolution
adjustment consists of changing the conversion result input from 8, 10 or 12 bits right aligned to a
12-bit word left aligned - refer to Section 27.7.6.5, ADC Resolution Selection Feature, for details.
When the CAL bit is asserted, this 14-bit data is the result of the calculations performed in the
1. In case the conversion result is routed through an on-chip DSP via side interface, the calibration is applied before the data
is sent to the DSP.
27-64
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor