PXR40RM Datasheet, PDF (502/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Software Watchdog Timer (SWT)
Table 18-4. SWT_TO Register Field Descriptions
Field
Description
0–31 Watchdog time-out period in clock cycles. An internal 32-bit down counter is loaded with this value or
WTO 0x100 which ever is greater when the service sequence is written or when the SWT is enabled.
18.3.2.4 SWT Window Register (SWT_WN)
The SWT Window (SWT_WN) register contains the 32-bit window start value. This register is cleared on
reset. This register is read only if either the SWT_MCR[HLK] or SWT_MCR[SLK] bits are set.
Offset 0x00C
Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
WST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-4. SWT Window Register (SWT_WN)
Table 18-5. SWT_WN Register Field Descriptions
Field
Description
0–31 Window start value. When window mode is enabled, the service sequence can only be written when the
WST internal down counter is less than this value.
18.3.2.5 SWT Service Register (SWT_SR)
The SWT Time-Out (SWT_SR) service register is the target for service operation writes used to reset the
watchdog timer.
Offset 0x010
Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
WSC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-5. SWT Service Register (SWT_SR)
18-6
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor