PXR40RM Datasheet, PDF (385/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Flash Memory Array and Control
NOTE
Lock and select are independent. If a block is selected and locked, no erase
will occur. See Section 12.2.2.2, Low/Mid Address Space Block Locking
Register (FLASH_x_LMLR), Section 12.2.2.3, High Address Space Block
Locking Register (FLASH_x_HLR), and Section 12.2.2.4, Secondary
Low/Mid Address Space Block Locking Register (FLASH_x_SLMLR), for
more information.
3. Write to any address in flash within the flash array A or B (i.e. if you intend to erase a B block, you
need to make sure the address is in array B). This is referred to as an erase interlock write.
4. Write a logic 1 to the FLASH_x_MCR[EHV] bit to start an internal erase sequence or skip to step
9 to terminate.
5. Wait until the FLASH_x_MCR[DONE] bit goes high.
6. Confirm FLASH_x_MCR[PEG] = 1.
7. Write a logic 0 to the FLASH_x_MCR[EHV] bit.
8. If more blocks are to be erased, return to step 2.
9. Write a logic 0 to the FLASH_x_MCR[ERS] bit to terminate the erase.
The erase sequence is presented graphically in Figure 12-18. The erase suspend operation detailed in
Figure 12-18 is discussed in section Section 12.3.5.1, Flash Erase Suspend/Resume.
After setting FLASH_x_MCR[ERS], one write (referred to as an interlock write) must be performed
before FLASH_x_MCR[EHV] can be set to a 1. Data words written during erase sequence interlock writes
are ignored. The user may terminate the erase sequence by clearing FLASH_x_MCR[ERS] before setting
FLASH_x_MCR[EHV].
An erase operation may be aborted by clearing FLASH_x_MCR[EHV] assuming
FLASH_x_MCR[DONE] is low, FLASH_x_MCR[EHV] is high, and FLASH_x_MCR[ESUS] is low. An
erase abort forces the module to step 8 of the erase sequence. An aborted erase will result in
FLASH_x_MCR[PEG] being set low, indicating a failed operation. The blocks being operated on before
the abort contain indeterminate data. The user may not abort an erase sequence while in erase suspend.
NOTE
Aborting an erase operation will leave the flash core blocks being erased in
an indeterminate data state. This may be recovered by executing an erase on
the affected blocks.
12.3.5.1 Flash Erase Suspend/Resume
The erase sequence may be suspended to allow read access to the flash core. The erase sequence may also
be suspended to program (erase-suspended program) the flash core. A program started during erase
suspend can be suspended. One erase suspend and one program suspend are allowed at a time during an
operation. It is not possible to erase during an erase suspend, or program during a program suspend. During
suspend, all reads to flash core locations targeted for program and blocks targeted for erase return
indeterminate data. Programming locations in blocks targeted for erase during erase-suspended program
may result in corrupted data.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
12-33