PXR40RM Datasheet, PDF (918/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
SCK
(CPOL = 0)
Master SOUT
1 ^LSB
Command Frame
Active Phase
Data Frame
Active Phase
0 Invalid
LSB
Invalid
PCS
t_DT
t_DT
t_DT = from 1 to 64 T_SCK
Command Frame = 4 to 32 bits
Data Frame = 4 to 32 bits
Selection Bit
Figure 25-38. TSB Downstream Frame
The Figure 25-38 shows the two types of downstream frames, command frame, and data frame, used in
the TSB configuration, refer to Section 25.4.9.1, PCS Switch Over Timing, and Section 25.4.9.3, TSB
Data Frame Format, for detailed information. The Command Word can be written by software, and the
Data Word consisting of 32 bits words, from the SDR or ASDR registers. Only the downstream frame is
supported in the TSB configuration, the upstream frame can be handled by software using any available
serial input.
The selection bit, the start bit for a frame, is not a requirement but could be implemented by software. The
number of the frame bits can be in the range of 4 to 32 bits. In this configuration the least significant bit
of a frame should be transmitted first (LSBFE = 1).
25.4.9.1 PCS Switch Over Timing
When in TSB mode it is possible to switch the set of PCS signals that are driven during the first part of the
frame to a different set of PCS signals during the second part of the frame. The bit at which this switch
over occurs is contained in the DSICR register.
In order to maximize both the setup and hold time margins on the old and new PCS signals the timing of
the switch over occurs on the active edge of the master SCK data capture between the last bit of the first
part of the frame and the first bit of the second part of the frame. For example, if the first part of the frame
is 5 bits and the second part of the frame is 10 bits the PCS signals will switch at the active edge of the
master SCK in between bits 5 and 6 of the frame as seen by the slave. The exact timing between the
external signals SCK and PCS signals will not be exactly aligned due to routing and pad differences. This
approach ensures that larger/shorter SCK periods will result in approximately symmetric
increases/decreases of setup and hold margins on the PCS signals. The setup time for the PCS signals
before the first bit of the first part of the frame and the hold time for the PCS signals after the last bit of
the second part of the frame are unchanged in this mode with respect to the other modes and remain
controlled by the CSC and ASC delay fields respectively when not in Continuous SCK mode.
25-58
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor