PXR40RM Datasheet, PDF (427/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
Table below lists register settings when a Debug interrupt is taken.
Table 13-30. Debug Interrupt—Register Settings
Register
Setting Description
CSRR0/
DSRR0¹
Set to the effective address of the excepting instruction for IAC, BRT, RET, CRET, and TRAP.
Set to the effective address of the next instruction to be executed following the excepting instruction for DAC
and ICMP.
For a UDE, IRPT, CIRPT, DCNT, or DEVT type exception, set to the effective address of the instruction that
the processor would have attempted to execute next if no exception conditions were present.
CSRR1/ Set to the contents of the MSR at the time of the interrupt
DSRR1
MSR
DBSR³
UCLE 0
SPE 0
WE 0
CE —/0²
EE —/0²
PR 0
Unconditional Debug Event:
Instr. Complete Debug Event:
Branch Taken Debug Event:
Interrupt Taken Debug Event:
Critical Interrupt Taken Debug Event:
Trap Instruction Debug Event:
Instruction Address Compare:
Data Address Compare:
Return Debug Event:
Critical Return Debug Event:
Debug Counter Event:
External Debug Event:
and optionally, an
Imprecise Debug Event flag
FP 0
ME —
FE0 0
DE 0
FE1 0
IS 0
DS 0
PMM 0
RI —
UDE
ICMP
BRT
IRPT
CIRPT
TRAP
{IAC1, IAC2, IAC3, IAC4}
{DAC1R, DAC1W, DAC2R, DAC2W}
RET
CRET
{DCNT1, DCNT2}
{DEVT1, DEVT2}
{IDE}
ESR
Unchanged
MCSR
Unchanged
DEAR
Unchanged
Vector
IVPR_0:15 || IVOR15_16:27 || 4b0000
1 _{assumes that the Debug interrupt is precise}
2 _{conditional based on control bits in HID0}
3 _{Note that multiple DBSR bits may be set}
13.9.17 SPE/EFPU APU Unavailable Interrupt (IVOR32)
The SPE APU Unavailable exception is taken if MSR_SPE is cleared and execution of a SPE or EFPU APU
instruction other than the scalar floating-point instructions or brinc is attempted. When the SPE/EFPU
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-39