PXR40RM Datasheet, PDF (718/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
While the protocol is in POC:config state, the application must program the offsets for the tables into the
Sync Frame Table Offset Register (SFTOR).
22.6.12.4 Sync Frame ID and Sync Frame Deviation Table Generation
The application controls the generation process of the Sync Frame ID and Sync Frame Deviation Tables
into the flexray memory using the Sync Frame Table Configuration, Control, Status Register (SFTCCSR).
A summary of the copy modes is given in Table 22-114.
Table 22-114. Sync Frame Table Generation Modes
SFTCCSR
OPT SDVEN SIDEN
Description
0
0
0 No Sync Frame Table copy
0
0
1 Sync Frame ID Tables will be copied continuously
0
1
0 Reserved
0
1
1 Sync Frame ID Tables and Sync Frame Deviation Tables will be copied continuously
1
0
0 No Sync Frame Table copy
1
0
1 Sync Frame ID Tables for next even-odd-cycle pair will be copied
0
1
0 Reserved
1
1
1 Sync Frame ID Tables and Sync Frame Deviation Tables for next even-odd-cycle pair will be
copied
The Sync Frame Table generation process is described in the following for the even cycle. The same
sequence applies to the odd cycle.
If the application has enabled the sync frame table generation by setting SFTCCSR.SIDEN to 1, the
controller starts the update of the even cycle related tables after the start of the NIT of the next even cycle.
The controller checks if the application has locked the tables by reading the SFTCCSR.ELKS lock status
bit. If this bit is set, the controller will not update the table in this cycle. If this bit is cleared, the controller
locks this table and starts the table update. To indicate that these tables are currently updated and may
contain inconsistent data, the controller clears the even table valid status bit SFTCCSR[EVAL]. Once all
table entries related to the even cycle have been transferred into the flexray memory, the controller sets the
even table valid bit SFTCCSR[EVAL] and the Even Cycle Table Written Interrupt Flag EVT_IF in the
Protocol Interrupt Flag Register 1 (PIFR1). If the interrupt enable flag EVT_IE is set, an interrupt request
is generated.
To read the generated tables, the application must lock the tables to prevent the controller from updating
these tables. The locking is initiated by writing a 1 to the even table lock trigger SFTCCSR.ELKT. When
the even table is not currently updated by the controller, the lock is granted and the even table lock status
bit SFTCCSR.ELKS is set. This indicates that the application has successfully locked the even sync tables
and the corresponding status information fields SFRA, SFRB in the Sync Frame Counter Register
(SFCNTR). The value in the SFTCCSR.CYCNUM field provides the number of the cycle that this table
is related to.
The number of available table entries per channel is provided in the SFCNTR.SFEVA and
SFCNTR.SFEVB fields. The application can now start to read the sync table data from the locations given
in Figure 22-144.
22-134
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor