PXR40RM Datasheet, PDF (166/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Field
16–23
24–31
EMFD
Table 6-3. ESYNCR1 Bit Field Descriptions (continued)
Description
Reserved.
Note: Do not set this bit to 1.
Enhanced Multiplication Factor Divider. The EMFD bits control the value of the divider in the PLL feedback
loop. The value specified by the EMFD bits establish the multiplication factor applied to the reference
frequency. The decimal equivalent of the EMFD binary number is substituted into the equation from
Table 6-10 for F_sys to determine the equivalent multiplication factor. The range of settings is
32  EMFD  132.
Note: EMFD values less than 32 and greater than 132 are invalid and cause the PLL to produce an
unpredictable clock output. The VCO frequency must be within the f_VCO specification (see the PXR40
Microcontroller Data Sheet).
When the EMFD bits are changed, the PLL loses lock. Do not change the EMFD bits during FM operation.
Before changing EMFD, FM must be disabled and then reconfigured after the PLL re-locks to the new EMFD
value.To prevent an immediate reset, clear the LOLRE bit before writing the EMFD bits.
In PLL Off mode, the EMFD bits have no effect.
Table 6-5 shows the available divide ratios.
Table 6-4. Pre-divider Ratios
EPREDIV
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010–1111
Input Divide Ratio (EPREDIV+1)
1
2 (default if PLLCFG[2]=0)
3
4 (default if PLLCFG[2]=1)
5
6
Invalid
8
Invalid
10
Invalid
Table 6-5. Feedback Divide Ratios
EMFD
0000_0000–0001_1111
0010_0000
0010_0001
0010_0010
0010_0011
0010_0100
Feedback Divide Ratio (EMFD+16)
Invalid
48 (default for PXR40)
49
50
51
52
PXR40 Microcontroller Reference Manual, Rev. 1
6-8
Freescale Semiconductor