PXR40RM Datasheet, PDF (1139/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
28.3 Functional Description
The following subsections describe the functional operation of a single block and apply to all Decimation
Filter blocks on the device.
28.3.1 Decimation Filter Input
The Decimation Filter receives input data from either the an eQADC block, or from the CPU using the
memory mapped DECFILT_x_IB register. The data source is selected by the
DECFILT_x_MCR[IO_SEL[1]] bit. Note that when the Decimation Filters are cascaded, filters other than
the head filter receive input from the adjacent filter. See Section 28.3.14, Cascade Mode, for more
information on cascade operation.
An interrupt or DMA request can be generated when the input buffer is empty, and the input data source
is the CPU or DMA. A DMA request is generated when the DECFILT_x_MCR[DSEL] = 1, and the input
buffer becomes empty. If DMA is not enabled, an interrupt is generated by setting the
DECFILT_x_MCR[IBIE] = 1. If both an interrupt and DMA request are enabled, the DMA takes
precedence.
An interrupt can also be generated when the input buffer is written with a new value. This interrupt is
enabled by the DECFILT_x_MCR[IDEN] bit. When enabled and data is written to the filter input buffer,
the DECFILT_x_MSR[IDF] bit is set. The IDF flag remains set, even after the input data has been
consumed by the filter and the buffer is free, until IDF is cleared by software write to the IDFC bit.
See Section 28.3.12, Interrupts and DMA Overview, for more information on interrupt and DMA requests.
28.3.1.1 Input Buffer Overrun
An input overrun occurs when the input buffer is holding input data and new data is received by the filter.
See Section 28.3.1, Decimation Filter Input, for details of the input buffer. When the decimation filter is
idle (DECFILT_x_MSR[BSY] = 0) the filter can receive two consecutive input buffer writes without input
overrun. Input buffer overrun is detected and flagged by the DECFILT_x_MSR[IVR] bit. The overrun
interrupt is enabled by the DECFILT_x_MCR[ERREN] bit.
The input buffer overrun can occur only in the following cases:
• When the input buffer has sample data to be processed but the filter is busy and another input (data
or timestamp) is received.
• When the input buffer has a timestamp, the internal timestamp register is loaded and the next input
data is received.
As an example of the input data sequence, assume that the filter is enabled and not busy, and all registers
are empty. Then a word of sample data is received followed by a timestamp and another word of sample
data. No input overrun occurs in this case, because the first sample is immediately transferred to the tap
input register, the timestamp is immediately transferred to the internal timestamp storage register, and the
second sample can be held in the input buffer until the end of the processing of the first sample data by the
filter. The input overrun may occur if more input is received before the end of the processing, or if the filter
is busy at the beginning of the received sequence.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-25