PXR40RM Datasheet, PDF (1152/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
for counter exception. These flags generate an error interrupt, if it is enabled (see Section 28.3.12,
Interrupts and DMA Overview).
The accumulator exception condition depends on whether it operates in saturated mode or not, as follows:
• In Saturated operation (DECFILTER_MXCR[SSAT] = 1): a sum exception occurs (SSE=1)
whenever an overflow is flagged; SSE asserts together with SSOVF.
• In Non-saturated operation (DECFILTER_MXCR[SSAT] = 0): a sum exception occurs (SSE=1)
when an overflow is flagged and DECFILTER_MXSR[SSOVF] is already set to 1.
• In Non-saturated operation, an accumulator exception also occurs if the accumulator overflows
twice without any update of the final integrator value DECFILTER_FINTVAL or the current
integrator counter DECFILTER_CINTCNT (by a read to the DECFILTER_CINTVAL register),
neither an integrator reset occurs. The SSOVF flag does not assert in this situation.
NOTE
The SSOVF flag can only be asserted upon a hardware request, a software
request, or when DECFILTER_CINTVAL is read, based on the internal
accumulator overflow state.
Similarly, the sample counter exception condition depends on whether it operates in saturated mode or not,
as follows:
• In Saturated operation (DECFILTER_MXCR[SCSAT] = 1): a counter exception occurs (SCE=1)
whenever an overflow is flagged; SCE asserts together with SCOVF.
• In Non-saturated operation (DECFILTER_MXCR[SCSAT] = 0): a counter exception occurs
(SCE=1) when an overflow is flagged and the DECFILTER_MXSR bit SCOVF is already set to 1.
• In Non-saturated operation, a counter exception also occurs if the counter overflows twice without
any update of the final count DECFILTER_FINTCNT or the current integrator counter
DECFILTER_CINTCNT (by a read to the DECFILTER_CINTVAL register), neither an
integration reset occurs. The SCOVF flag does not assert in this situation.
NOTE
The SCOVF flag can only be asserted upon a hardware request, a software
request, or when DECFILTER_CINTVAL is read (also updating
DECFILTER_CINTCNT), based on the internal counter overflow state.
28.3.14 Cascade Mode
Cascade mode is a configuration of the decimation filters where two or more filters are chained together
serially to provide more complex filtering functions. All filters in the cascade arrangement are configured
to operate in cascade mode using the CASCD[1:0] field in the DECFILT_x_MCR register. Figure 28-18
shows an example of a simple cascaded arrangement. This example shows the eQADC being used for both
data input and output, but cascaded filters may also be configured to receive data from the CPU/DMA. The
‘head’ receives the raw data to be filtered from the eQADC. The bottom block, or ‘tail’, is the last filter
block in the chain. It sends the output result to the selected data destination. The blocks in between, or
‘middle’ blocks, do not exchange data (receive/transmit) with the eQADC (or CPU/DMA), only with the
28-38
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor