PXR40RM Datasheet, PDF (758/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
Table 23-9. MODE Bits (continued)
MODE
101_0101
101_0110
Mode
MCB
MCB
101_0111
MCB
101_1000
101_1001
101_1010
101_1011
101_1100
OPWFMB
Reserved
OPWFMB
Reserved
OPWMCB
101_1101
OPWMCB
101_1110
OPWMCB
101_1111
OPWMCB
110_0000
OPWMB
110_0001
Reserved
110_0010
OPWMB
110_0011 – 111_1111 Reserved
Description
Modulus Counter Buffered (Up/Down counter with flag on A match, external clock)
Modulus Counter Buffered (Up/Down counter with flag on A match or cycle boundary,
internal clock)
Modulus Counter Buffered (Up/Down counter with flag on A match or cycle boundary,
external clock)
Output Pulse Width and Frequency Modulation Buffered, (flag on B match)
Output Pulse Width and Frequency Modulation Buffered, (flag on A or B matches)
Center Aligned Output Pulse Width Modulation Buffered
(flag in trailing edge, trailing edge dead time)
Center Aligned Output Pulse Width Modulation Buffered
(flag in trailing edge, leading edge dead time)
Center Aligned Output Pulse Width Modulation Buffered
(flag in both edges, trailing edge dead time)
Center Aligned Output Pulse Width Modulation Buffered
(flag in both edges, leading edge dead time)
Output Pulse Width Modulation Buffered (flag on B match)
Output Pulse Width Modulation Buffered (flag on A or B matches)
23.3.2.8 eMIOS200 Status Register (EMIOS_CSR[n])
Offset: UC[n] base address + 0x0010
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R OVR 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
R OVFL 0
W w1c
Reset 0
0
18
19
20
21
22
23
24
25
26
27
28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-9. eMIOS200 Status Register (EMIOS_CSR[n])
29
30
31
UCIN UCOUT FLAG
w1c
0
0
0
23-18
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor