PXR40RM Datasheet, PDF (448/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Peripheral Bridge (PBRIDGE)
• Supports 32-bit slave peripherals. Byte, 16-bit halfword, and 32-bit word reads and
writes are supported to each slave peripheral.
• Supports a pair of slave accesses for 64-bit instruction fetches.
• Provides configurable per-module write buffering support.
• Provides configurable per-module and per-master access protections.
15.1.4 Modes of Operation
The PBRIDGE has only one operating mode.
15.2 External Signal Description
The PBRIDGE has no external signals.
15.3 Memory Map and Register Definitions
The memory map for the 32-bit PBRIDGE A registers is shown in Table 15-2.
Table 15-2. PBRIDGE A Memory Map
Address
Base (0xC3F0_0000)
Base + (0x0004–0x001F)
Base + 0x0020
Base + (0x0024–0x003F)
Base + 0x0040
Base + 0x0044
Base + 0x0048
Base + 0x004C
Base + (0x0050–0x0053)
Register
Bits Access Reset Value Section/Page
PBRIDGE_A_MPCR—Master privilege control 32
register
Reserved
PBRIDGE_A_PACR0—Peripheral access
32
control register 0
Reserved
PBRIDGE_A_OPACR0—Off-platform
32
peripheral access control register 0
PBRIDGE_A_OPACR1—Off-platform
32
peripheral access control register 1
PBRIDGE_A_OPACR2—Off-platform
32
peripheral access control register 2
PBRIDGE_A_OPACR3—Off-platform
32
peripheral access control register 3
Reserved
R/W 0x7777_7777 15.3.1.1/15-6
R/W 0x5444_4444 15.3.1.2/15-7
R/W 0x4444_4444 15.3.1.2/15-7
R/W 0x4444_4444 15.3.1.2/15-7
R/W 0x4444_4444 15.3.1.2/15-7
R/W 0x4444_4444 15.3.1.2/15-7
15-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor