PXR40RM Datasheet, PDF (1268/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
30.2.2 Address/Data Bus Configurations
Table 30-3 shows the function of the external pins in each of the possible muxed/non-muxed usage
configurations allowed for this device.
Table 30-3. Function of EBI Pins for All Possible Configurations
Mode
D_WE[0:3]
D_ADD[9:15]
D_ADD[16:30]¹
D_ADD_DAT[16:30]²
D_ADD_DAT
[0:15]
D_CS2³
Non-muxed 16-bit mode write/byte enable [0:1] Address 9:15
Address 16:30
Data 0:15
Address 31
Muxed 32-bit mode write/byte enable [0:3]
Not used
Address 16:30 / Data
16:30
Address 0:15 /
Data 0:15
Address 31 / Data 31
Muxed 16-bit mode
(EBI_MCR[D16_31]=1)
write/byte enable [0:1]
Address 9:15
Address 16:30 / Data
0:14
Not used
Address 31 / Data 15
Muxed 16-bit mode
(EBI_MCR[D16_31]=0)
write/byte enable [0:1]
Address 9:15
Not used
Address 16:31 /
Data 0:15
Not used
1 _{D_ADD[16:30] SIU PCR functionality must be selected in non-multiplexed mode (AD_MUX = 0)}
2 _{D_ADD_DAT[16:30] SIU PCR functionality must be selected in multiplexed mode (AD_MUX = 1)}
3 _{D_CS2 is the primary function. Secondary function is EBI data only in non-mux mode and address/data in mux mode.}
30.2.3 Detailed Signal Descriptions
30.2.3.1 D_ADD [9:30] — Address Lines 9-30
The D_ADD[9:30] signals specify the physical address of the bus transaction.
The 22 address lines correspond to bits 3-31 of the EBI’s 32-bit internal address bus.
30.2.3.2 D_BDIP — Burst Data in Progress
D_BDIP is asserted to indicate that the master is requesting another data beat following the current one.
This signal is driven by the EBI on all EBI-mastered external burst cycles, but is only sampled by burst
mode memories that have a corresponding pin. See Section 30.4.2.5, Burst Transfer.
30.2.3.3 D_CLKOUT — Clockout
D_CLKOUT is a general-purpose clock output signal to connect to the clock input of SDR external
memories and in some cases to the input clock of another MCU in multi-master configurations.
30.2.3.4 CAL_CS [0:3] — Calibration Chip Selects 0-3
CAL_CSx is asserted by the master to indicate that this transaction is targeted for a particular memory
bank on the Calibration external bus.
The calibration chip selects are driven only by the EBI. External master accesses on the Calibration bus
are not supported. In all other aspects, the calibration chip-selects behave exactly as the primary
chip-selects. See Section 30.4.1.4, Memory Controller with Support for Various Memory Types for details
on chip-select operation.
30-6
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor