PXR40RM Datasheet, PDF (162/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Table 6-1. FMPLL Memory Map (continued)
Offset from
FMPLL_BASE_ADDR
(0xC3F8_0000)
Register
0x0008
ESYNCR1—FMPLL enhanced synthesizer
control register 1
0x000C
ESYNCR2—FMPLL enhanced synthesizer
control register 2
0x0010–0x001C Reserved
0x20
SYNFMCR—FMPLL synthesizer FM control
register
1 _{See specific register description.}
Bits Access Reset Value Section/Page
32 R/W 0x8001_0053 6.3.2.2/6-7
32 R/W 0x0000_0005 6.3.2.3/6-9
32 R/W
—¹
6.3.2.4/6-12
6.3.2 Register Descriptions
This section lists the FMPLL registers in address order and describes the registers and their bit fields.
6.3.2.1 FMPLL Synthesizer Status Register (SYNSR)
Offset: FMPLL_BASE_ADDR + 0x0004
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
LOLF
LOC MODE
PLL
SEL
PLL
REF
LOCKS LOCK LOCF
U¹
U¹
W
w1c
w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-3. FMPLL Synthesizer Status Register (SYNSR)
1 _{These bits may read 0 or 1, depending on current state of the PLL, however they do not provide any useful user information.}
Field
0–21
Reserved
Table 6-2. SYNSR Bit Field Descriptions
Description
PXR40 Microcontroller Reference Manual, Rev. 1
6-4
Freescale Semiconductor