PXR40RM Datasheet, PDF (1054/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
enable trigger for the Repeat trigger. This means it is necessary to have an Advance trigger first to enable
the detection of the Repeat trigger. When the Repeat trigger is enabled, the Advance trigger is used to
advance the pop pointer beyond some loop sub-queue. And it is to disable the Repeat trigger by executing
a Pause without a previous REP bit.
A typical sequence of events is presented below to describe the relationship between the triggers.
In Streaming mode, the CFIFO0 is filled with CCWs using the DMA as usual. The two triggers are
configured to positive edge and single scan mode.
The SSS bit is asserted and the trigger detector of the Repeat trigger is disabled in the start of the queue.
It is necessary to receive the first Advance trigger to enable the detector of the other trigger. This enable
is useful when the Repeat trigger is received all the time and the trigger signal can be disabled when it is
not desired.
The Advance trigger is received and detected and the Repeat trigger detector is enabled. No commands are
executed until now.
The Repeat trigger is detected and the commands start to be executed in sequence. If a REP bit is decoded
with the PAUSE bit, the loop is configured and the CFIFO0 commands stop to be executed. The next
Repeat trigger is waited to start the execution of the loop again, or the Advance trigger can be detected to
break the loop and advance the queue in CFIFO0. The Repeat trigger detector remains enabled.
If the Advance trigger is received and the next command in the CFIFO0 does not present the REP bit set,
this means the CFIFO0 is not starting a new loop. In this case (outside a loop) if a PAUSE bit is decoded,
this means to disable the Repeat trigger detector. This can be useful if the Repeat trigger is not required for
some interval of time. The Repeat trigger detector is enabled again when the next Advance trigger event
is detected.
27.7.4.2.3 CFIFO0 Diagram Description in Streaming Mode
Figure 27-51 represents the main components of CFIFO0 in streaming mode. However, some signals
behave in a different way from the common operation. The Push Next Data Pointer points to the next
available CFIFO0 location for storing data written into the EQADC Command FIFO Push Register. The
Transfer Next Data Pointer points to the next entry to be transferred to Cbuffer. The Repeat Pointer points
to the first entry of the repeating sub-queue. TNXTPTR in Section 27.6.2.7, EQADC FIFO and Interrupt
Status Registers (EQADC_FISR), indicates the index of the entry that is currently being addressed by the
Transfer Next Data Pointer, and CFCTR, in the same register, provides the number of entries stored in the
CFIFO.
When CFS0 in Section 27.6.2.10, EQADC CFIFO Status Register (EQADC_CFSR), is TRIGGERED, the
EQADC generates the proper control signals for the transfer of the entry pointed by Transfer Next Data
Pointer. CFUF0 in Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is set
when CFIFO0 underflow event occurs. A CFIFO underflow occurs when the CFIFO is in TRIGGERED
state and it is empty. No commands will be transferred from an underflowing CFIFO, nor will command
transfers from lower priority CFIFOs be blocked. CFIFO0 is empty when CFCTR0 is zero. CFIFO0 is full
when (CFCTR0 mod CFIFO_DEPTH) is zero but CFCTR0 is not zero.
When the EQADC completes the transfer of an entry from CFIFO0 in loop condition: the transferred entry
is not popped from CFIFO0, the CFIFO counter CFCTR in the Section 27.6.2.7, EQADC FIFO and
27-72
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor