PXR40RM Datasheet, PDF (1002/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Address: 0x0050 (CFIFO0)
0x0052 (CFIFO1)
0x0054 (CFIFO2)
0x0056 (CFIFO3)
0x0058 (CFIFO4)
0x005A (CFIFO5)
Access: User read/write
0123
4
5
6
7
8
9 10 11 12 13 14 15
R0
0
0 _{CFE STR} 0
0
0
W
EE0* ME0* _{SSEx CFINVx}
MODEx
AMODE0*
Reset 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
* only available for CFIFO0
Figure 27-7. EQADC CFIFO Control Register x (EQADC_CFCRx)
Table 27-10. EQADC_CFCRx Field Description
Field
Description
0–2 Reserved
3
CFEEE0
CFIFO0 Entry Number Extension Enable. The CFEEE0 bit is used to enable the extension of the CFIFO0 entries.
When in extended mode, the CFIFO0 total entries is the sum of normal entries plus the defined value for extension.
For more details, refer to Section 27.7.4.2, CFIFO0 Streaming Mode Description.
1 Enable the extension of CFIFO0 entries.
0 CFIFO0 has a normal value of entries.
4
STRME0
CFIFO0 Streaming Mode Operation Enable. The STRME0 bit is used to enable the streaming mode of operation
of CFIFO0. In this case, it is possible to repeat some sequence of commands of this FIFO without having to load
new commands from a command queue. For more details, refer to Section 27.7.4.2, CFIFO0 Streaming Mode
Description.
1 Enable the streaming mode of CFIFO0.
0 Streaming mode of CFIFO0 is disabled.
5
SSEx
CFIFO Single-Scan Enable Bit x. The SSEx bit is used to set the EQADC_FISR[SSSx] bit. Writing a “1” to SSEx
will set the EQADC_FISR[SSSx] field if the CFIFO is in single-scan mode. When EQADC_FISR[SSSx] is already
asserted, writing a “1” to SSEx has no effect. If the CFIFO is in continuous-scan mode or is disabled, writing a “1”
to SSEx will not set EQADC_FISR[SSSx]. Writing a “0” to SSEx has no effect. SSEx always is read as “0”.
6
CFINVx
0 No effect.
1 Set the SSSx bit.
CFIFO Invalidate Bit x. The CFINVx bit causes the EQADC to invalidate all entries of CFIFOx. Writing a “1” to
CFINVx will reset the value of EQADC_FISR[CFCTRx]. Writing a “1” to CFINVx also resets the Push Next Data
Pointer, Transfer Next Data Pointer to the first entry of CFIFOx in Figure 27-49. CFINVx always is read as “0”.
Writing a “0” has no effect.
0 No effect.1Invalidate all of the entries in the corresponding CFIFO.
Note: Writing CFINVx only invalidates commands stored in CFIFOx; previously transferred commands that are
waiting for execution, that is commands stored in the CBuffers, will still be executed, and results generated
by them will be stored in the appropriate RFIFO.
Note: CFINVx must not be written unless the MODEx is configured to disabled, and CFIFO status is IDLE.
7
Reserved
27-20
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor