PXR40RM Datasheet, PDF (165/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
6.3.2.2 FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1)
This is one of two FMPLL synthesizer control registers that are used to access enhanced features in the
FMPLL. The bit fields in the ESYNCR1 behave as described in Figure 6-4.
Offset: FMPLL_BASE_ADDR + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R1
W
CLKCFG[2:0]
0
0
0
0
0
00 0
EPREDIV
Reset 1
—¹ —¹ —¹
0
0
0
0
0
00 0
0
0 —² 1
16
R0
W 0³
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
EMFD
Reset 0
0
0
0
0
0
0
0
0
01 0
0
0
0
0
1 _{Reset value determined by PLLCFG pins during reset.}
2 _{Resets to value of PLLCFG[2] (0 if PLLCFG[2]=0; 1 if PLLCFG[2]= 1)}
3 _{Do not set this bit to 1.}
Figure 6-4. FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1)
Table 6-3. ESYNCR1 Bit Field Descriptions
Field
Description
0
1–3
CLKCFG[2:0]
4–11
12–15
EPREDIV
Reserved.
Note: This bit is set to 1 on reset and always reads as 1. Writes to this bit have no effect.
Clock Configuration. The CLKCFG[2:0] bits are writable versions of the MODE, PLLSEL, and PLLREF bits
in the SYNSR. These change the clock mode, after reset has negated, via software. CLKCFG[2:0] map
directly to MODE, PLLSEL, and PLLREF to control the system clock mode.
Note: CLKCFG = 0b101 (or any reserved/invalid value) can produce an unpredictable clock output.
Note: The ESYNCR2[LOLRE] and ESYNCR2[LOCRE] should be set to 0 before changing the PLL mode,
so that a reset is not immediately generated when CLKCFG is written.
Reserved
Enhanced Pre-Divider. The EPREDIV bits control the value of the divider on the input clock. The output of
the pre-divider circuit generates the reference clock to the PLL analog loop. The decimal equivalent of the
EPREDIV binary number is substituted into the equation from Table 6-8.
Note: Setting EPREDIV to any of the invalid states in Table 6-4 causes the PLL to produce an unpredictable
output clock. The output frequency of the divider must equal f_pllref (see the PXR40 Microcontroller Data
Sheet).
When the EPREDIV bits are changed, the PLL immediately loses lock. Do not change the EPREDIV bits
during FM operation. Before changing EPREDIV, FM must be disabled and then reconfigured after the PLL
re-locks to the new EPREDIV value. To prevent an immediate reset, clear the LOLRE bit before writing the
EPREDIV bits. In PLL Off mode, the EPREDIV bits have no effect.
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
6-7