PXR40RM Datasheet, PDF (728/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
22.6.19.1 System Bus Illegal Address Access
If the system bus detects an controller access to an illegal address, the controller receives a notification
from the system bus about this event and sets the ILSA_EF flag in the CHI Error Flag Register
(CHIERFR).
22.6.19.2 System Bus Access Timeout
The controller starts a timer when it has send an access request to the system bus. This timer expires after
2 * SYMATOR.TIMEOUT + 2 system bus clock cycles. If the access is not finished within this amount
of time, the SBCF_EF flag in the CHI Error Flag Register (CHIERFR) is set.
22.6.19.3 Continue after System Bus Failure
If the SBFF bit in the Module Configuration Register (MCR) is 0, the controller will continue its operation
after the occurrence of the system bus access failure but will not generate any system bus accesses until
the start of the next communication cycle.
If a frame is under transmission when the system bus failure occurs, a correct frame is generated with the
remaining header and frame data are replaced by all zeros. Depending on the point in time this can affect
the PPI bit, the Header CRC, the Payload Length in case of an dynamic slot, and the payload data. Starting
from the next slot in the current cycle, no frames will be transmitted and received, except for the key slot,
where a sync or startup null-frame is transmitted, if the key slot is assigned.
If a frame is received when the system bus failure occurs, the reception is aborted and the related receive
message buffer is not updated.
Normal operation is resumed after the start of next communication cycle.
22.6.19.4 Freeze after System Bus Failure
If the SBFF bit in the Module Configuration Register (MCR) is set to 1, the controller will go into the
freeze mode immediately after the occurrence of one of the system bus access failures.
22.6.20 Interrupt Support
The controller provides 172 individual interrupt sources and five combined interrupt sources.
22.6.20.1 Individual Interrupt Sources
22.6.20.1.1 Message Buffer Interrupts
The controller provides 128 message buffer interrupt sources.
Each individual message buffer provides an interrupt flag MBCCSn[MBIF] and an interrupt enable bit
MBCCSn[MBIE]. The controller sets the interrupt flag when the slot status of the message buffer was
updated. If the interrupt enable bit is asserted, an interrupt request is generated.
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor