PXR40RM Datasheet, PDF (547/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
21.3.2.5 eDMA Set Enable Request Register (EDMA_x_SERQR)
NOTE
Any reference to EDMA_A_[register_name] should be ignored when using
eDMA_B. That register does not exist in eDMA_B. Registers that exist in
both eDMA_A and eDMA_B are indicated with a register name of format
EDMA_x_[register_name].
The EDMA_x_SERQR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_A_ERQRH or EDMA_x_ERQRL to enable the eDMA request for a given channel. The data
value on a register write causes the corresponding bit in the EDMA_A_ERQRH or EDMA_x_ERQRL to
be set. Setting bit 1 (SERQ[0]) provides a global set function, forcing the entire contents of
EDMA_A_ERQRH and EDMA_x_ERQRL to be asserted. Reads of this register return all zeroes.
If bit 0 is set, the SERQ command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_x_BASE + 0x0018
Access: User write-only
0
1
2
3
4
5
6
7
R0
0
0
0
0
0
0
0
W NOP
SERQ[0:6]
Reset 0
0
0
0
0
0
0
0
Figure 21-9. eDMA Set Enable Request Register (EDMA_x_SERQR)
Table 21-8. EDMA_x_SERQR Field Descriptions
Field
0
NOP
1–7
SERQ
Descriptions
No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
Set Enable Request.
0–31 (63 for eDMA_A) Set corresponding bit in EDMA_A_ERQRH or EDMA_x_ERQRL.
64–127 Set all bits in EDMA_A_ERQRH and EDMA_x_ERQRL.
Bit 2 (SERQR[1]) is not used on eDMA_B.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-23