PXR40RM Datasheet, PDF (755/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Field
21–22
BSL
23
EDSEL
Enhanced Modular Input/Output Subsystem (eMIOS200)
Table 23-8. EMIOS_CCR[n] Field Descriptions (continued)
Description
Bus Select Bits. The BSL bits are used to select either one of the counter buses or the internal counter to be
used by the unified channel.
BSL
00
01
10
11
Selected Bus
All channels: counter bus[A]
Channels 0 to 7: counter bus[B]
Channels 8 to 15: counter bus[C]
Channels 16 to 23: counter bus[D]
Channels 24 to 31: counter bus[E]
Reserved
All channels: internal counter
Edge Selection Bit. For input modes, the EDSEL bit selects if the internal counter is triggered by both edges
of a pulse or by a single edge only as defined by the EDPOL bit. When not shown in the mode of operation
description, this bit has no effect.
0 Single edge triggering defined by the EDPOL bit.
1 Both edges triggering.
For GPIO in mode, the EDSEL bit selects if a FLAG can be generated.
0 A FLAG is generated as defined by the EDPOL bit.
1 No FLAG is generated.
For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match.
0 The EDPOL value is transferred to the output flip-flop.
1 The output flip-flop is toggled.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-15