PXR40RM Datasheet, PDF (1033/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Field
6
FMTA
7
8–9
RESSEL
10–13
14–15
PRE_GAIN
Enhanced Queued Analog-to-Digital Converter (EQADC)
Table 27-28. ADC_ACR1-8 Field Descriptions (continued)
Description
Conversion Data Format for Alternate Configuration. If the DEST field is not 0b000, the FMTA bit specifies
how the 12-bit conversion data returned by the ADCs is formatted into the 16-bit data which is sent to the
parallel side interface.
0 Right justified unsigned
1 Right justified signed
Reserved
ADC Resolution Selection.
00 ADC set to 12-bits resolution
01 ADC set to 10-bits resolution
10 ADC set to 8-bits resolution
11 Reserved
Reserved
ADC Pre-gain control. The PRE_GAIN[0:1] controls the gain of the ADC input stage by changing the
internal ADC iterations in the gain stage.
00 X1 gain
01 X2 gain
10 X4 gain
11 Reserved
27.6.3.7 ADC0/1 Alternate Gain Registers (ADC0_AGR1-2 and ADC1_AGR1-2)
The Alternate Gain Registers (ADC0_AGRx and ADC1_AGRx, x=1-2) contain the gain calibration
constants used to fine-tune the ADCs conversion results for alternate configurations 1 or 2. A conversion
from an ADC uses the corresponding ADC0_AGRx or ADC1_AGRx register when the conversion
command (with the alternate configuration format) is written to an address in the range 0x08-0x09 of the
on-chip ADC memory map. Refer to Section 27.7.6.6, ADC Calibration Feature, for details about the
calibration scheme used in the EQADC.
ADC0 Register Address: 0x31, 0x35
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
W
ALTGCC0x
Reset 0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC1 Register Address: 0x31, 0x35
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
W
ALTGCC1x
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-39. ADC0/1 Alternate x Gain Register (ADC0/1_AGRx, x=1-2)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-51