PXR40RM Datasheet, PDF (1216/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
• Thread Length Mode: the watchdog count is reset at the end of each thread.
• Busy Length Mode: the watchdog count is reset when the microengine goes idle. A sequence of
threads, one right after another, keeps the count running. The counter is also reinitialized when a
thread is forced to end, so that a new count begins if another TST initiates at the following
microcycle.
The following applies to the watchdog mechanism:
• Microcycles during TST and SDM access wait-states (on TST or instruction execution) are
counted.
• If the watchdog count equals WDCNT in the last microinstruction (with SDM wait-states or not)
of a thread servicing a channel.
• If the watchdog count expires (gets greater than WDCNT) during the TST, the thread is forced end
on its first instruction.
• The watchdog count does not wrap, so that a thread (in thread length mode) or a thread sequence
(in busy length mode) that lasts for more than the maximum value of WDCNT does get a forced
end.
NOTE
Watchdog must not be enabled when the microengine enters halt mode. The
counter does not run when the engine is stopped, and resets when the
watchdog is disabled.
29.3.2 Host Interface
29.3.2.1 System Configuration
System Configuration Registers are described in Section 29.2.5, System Configuration Registers. Detailed
explanation on the configured functionalities is found throughout Section 29.3, Functional Description.
29.3.2.2 Interrupts and Data Transfer Requests
29.3.2.2.1 Interrupt Types and Sources
Each one of the eTPU channels can be a source of two requests: Channel Interrupt request and Data
Transfer Request. Channel Interrupts are targeted to a Host CPU. Data Transfer Requests may be targeted
to a data transfer module (e.g., a DMA controller). Interrupt and Data Transfer registers are used by the
Host to enable interrupts and data transfer requests, indicate their status and service them. Interrupt and
Data Transfer requests have the same sets of registers and external signals, and are handled in the same
way. They differ only by the fact that Data Transfer Requests are also cleared by the assertion of respective
DMA completion acknowledge line. Data Transfer Requests can be used as another source for Host
interrupts at MCU integration if not used with a DMA.
29-48
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor