PXR40RM Datasheet, PDF (510/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Timer Module (STM)
19.3.2.2 STM Count Register (STM_CNT)
The STM Count Register (STM_CNT) holds the timer count value.
Offset 0x004
Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-2. STM Count Register (STM_CNT)
Table 19-3. STM_CNT Field Descriptions
Field
Description
0–31 Timer count value used as the time base for all channels. When enabled, the counter increments at the
CNT rate of the system clock divided by the prescale value.
19.3.2.3 STM Channel Control Register (STM_CCRn)
The STM Channel Control Register (STM_CCRn) has the enable bit for channel n of the timer.
Offset 0x10+0x10*n
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-3. STM Channel Control Register (STM_CCRn)
Table 19-4. STM_CCRn Field Descriptions
Field
Description
0–30
31
CEN
Reserved
Channel Enable.
0 = The channel is disabled.
1 = The channel is enabled.
19-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor