PXR40RM Datasheet, PDF (414/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
Table 13-13. Machine Check Syndrome Register (MCSR) (continued)
Field
Description
Exception
Type¹
Recoverable
Load type instruction Error Report
Error
Precise
16
LD
An error occurred during the attempt to execute the load Report
type instruction located at the address stored in
MCSRR0. This could be due to a parity error or an
external bus error.
Store type instruction Error Report
Error
Precise
17
ST
An error occurred during the attempt to execute the
store type instruction located at the address stored in
MCSRR0. This could be due to a parity error, or on
Report
certain external bus errors.
Guarded instruction Error Report
Error
Precise
18
G
An error occurred during the attempt to execute the load Report
or store type instruction located at the address stored in
MCSRR0 and the access was guarded and
encountered an error on the external bus.
19–25
Reserved, should be cleared.
—
26
SNPERR
Snoop Lookup Error
Async Mchk Unlikely?
An error occurred during certain snoop operations. This
is typically due to a data cache tag parity error, in which
case DC_TPERR will also be set.
27
BUS_IRERR
Read bus error on Instruction fetch or linefill
Async Mchk Precise if data
used
28
BUS_DRERR
Read bus error on data load or linefill
Async Mchk Precise if data
used
29
BUS_WRERR
Write bus error on store or cache line push
Async Mchk Unlikely
30–31
Reserved, should be cleared.
—
1 _{The Exception Type indicates the exception type associated with a given syndrome bit}
- “Error Report” indicates that this bit is only set for error report exceptions which cause machine
check interrupts. These bits are only updated when the machine check interrupt is actually taken.
Error report exceptions are not gated by MSR_ME. These are synchronous exceptions. These bits will
remain set until cleared by software writing a “1” to the bit position(s) to be cleared.
- “Status” indicates that this bit is provides additional status information regarding the logging of a
machine check exception. These bits will remain set until cleared by software writing a “1” to the bit
position(s) to be cleared.
- “NMI” indicates that this bit is only set for the non-maskable interrupt type exception which causes a
machine check interrupt. This bit is only updated when the machine check interrupt is actually taken.
NMI exceptions are not gated by MSR_ME. This is an asynchronous exception. This bit will remain set
until cleared by software writing a “1” to the bit position.
- “Async Mchk” indicates that this bit is set for an asynchronous machine check exception. These bits
are set immediately upon detection of the error. Once any “Async Mchk” bit is set in the MCSR, a
machine check interrupt will occur if MSR_ME=1. If MSR_ME=0, the machine check exception will remain
pending. These bits will remain set until cleared by software writing a “1” to the bit position(s) to be
cleared.
13-26
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor