PXR40RM Datasheet, PDF (410/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
Table 13-12. ESR Bit Settings (continued)
Field
Description
Associated Interrupt Type
SPE/EFPU APU Operation
24
SPE
25 Reserved
VLE Mode Instruction
26
VLEMI
27–29
30
MIF
31
Reserved
Misaligned Instruction Fetch
Reserved
SPE/EFPU Unavailable
EFPU Floating-point Data
Exception
EFPU Floating-point Round
Exception
Alignment
Data Storage
Data TLB
—
SPE/EFPU Unavailable
EFPU Floating-point Data
Exception
EFPU Floating-point Round
Exception
Data Storage
Data TLB
Instruction Storage
Alignment
Program
System Call
—
Instruction Storage
Instruction TLB
—
13.6 Machine State Register
The Machine State Register defines the state of the processor.
0
0
0
00
00
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Read/ Write; Reset - 0x0
The MSR bits are defined below.
Field
0–4
5
UCLE
Description
Reserved¹
User Cache Lock Enable
0 - Execution of the cache locking instructions in user mode (MSR_PR=1) disabled; DSI
exception taken instead, and ILK or DLK set in ESR.
1 - Execution of the cache lock instructions in user mode enabled.
13-22
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor