PXR40RM Datasheet, PDF (1307/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
The timing diagrams and protocol for the calibration bus is identical to the primary bus, except that some
signals are missing on the calibration bus.
There is an inherent dead cycle between a calibration chip-select access and a non-calibration access
(chip-select or non-chip-select), just like the one between accesses to two different non-calibration
chip-selects (described in Section 30.4.2.4.3, Back-to-Back Accesses).
Figure 30-36 shows an example of a non-calibration chip-select read access followed by a calibration
chip-select read access. Note that this figure is identical to Figure 30-18, except the CSy is replaced by
CAL_CSy. Timing for other cases on calibration bus can similarly be derived from other figures in this
document (by replacing CS with CAL_CS).
D_CLKOUT
D_ADD[9:30]
D_RD_WR
D_BDIP
D_TS
D_ADD_DAT[0:31]
D_TA
CS[n]
D_ADD_DAT is valid
D_ADD_DAT is valid
CAL_CS[y]
D_OE
Figure 30-36. Back-to-Back 32-bit Reads to CS, CAL_CS Banks
30.4.2.11 Misaligned Access Support
This section describes all the misaligned cases supported by the EBI. These cases are a subset of the full
set of cases allowed by the AMBA AHB V6 specification. The EBI works under the assumption that all
internal masters on the device do not produce any misaligned access cases (to the EBI) other than the ones
below.
30.4.2.11.1 Misaligned Access Support (64 bit AMBA)
Table 30-20 shows all the misaligned access cases supported by the EBI (using a 64-bit AMBA
implementation), as seen on the internal master AMBA bus. All other misaligned cases are not supported.
If an unsupported misaligned access to the EBI is attempted (such as non-chip-select or burst misaligned
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
30-45