PXR40RM Datasheet, PDF (1118/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
28.1.1 Features
The decimation filter block includes these features:
• Selectable 4th order IIR filter, or 8th order FIR filter
— 16-bit, two’s complement signed input/output data
— Internal taps with 16-bit (feed-forward taps) and 24-bit (feedback taps) resolutions (fixed point)
for two’s complement signed value
— 24-bit programmable filter coefficients (fixed point) for two’s complement signed value
— MAC unit with 51-bit fixed point accumulator
— Convergent rounding methodology
— Two’s complement overflow or saturation selection
— 58 system (core frequency divided by two) clock cycles to process the input
• Direct data input from the on-chip eQADC_A and eQADC_B block
• DMA access to input and output data buffers
• CPU accessible status/configuration registers and data input/output
• Filter initialization (flush) and stabilization (prefill) commands
• Timestamp support
• Programmable integer decimation rates of 1 to 16
• 32-bit, fixed point, signed or unsigned integrator unit with hardware triggered windowing
• Cascading of two or more blocks to create more complex filters
28.1.2 Modes of Operation Overview
This section provides an overview of the operational modes of the Decimation Filter. The modes are
selected using the Module Configuration Register fields MDIS, FREN, and FRZ (see Section 28.2.2.1,
Decimation Filter Module Configuration Register (DECFILT_x_MCR). The mode selection is
summarized in Table 28-1.
Table 28-1. Operation Mode Selection
Mode
MDIS
FREN, FRZ
Normal
Freeze
Disabled
0
(0,0), (0,1) or (1,0)
0
1, 1
1
X
28.1.2.1 Normal Mode
This is the default operational mode of the Decimation Filter. In this mode, the Decimation Filter processes
each new input in the input buffer according the filter, decimator, and integrator configuration.
28-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor