PXR40RM Datasheet, PDF (356/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Flash Memory Array and Control
• Software programmable block program/erase restriction control for low, mid and high address
spaces.
• Erase of selected block(s).
• Read page size of 128 bits (low/mid-address space) and 256 bits (for high-address space).
• ECC with single-bit correction, single-bit detection, and double-bit detection.
• Minimum program size is 2 consecutive 32 bit words, aligned on a 0-modulo-8 byte address, due
to ECC.
• Embedded hardware program and erase algorithm.
• Read while Write with multiple partitions.
• Erase suspend, program suspend and erase-suspended program.
• Automotive flash which meets automotive endurance and reliability requirements.
• Shadow information stored in non-volatile shadow block.
• Independent program/erase of the shadow block.
12.1.3 Modes of Operation
12.1.3.1 Flash User Mode
User mode is the default operating mode of the flash module. In this mode, it is possible to read and write,
program and erase the flash module.
12.1.3.2 User Test Mode
User Test (UTest) mode is where a portion of the Freescale test modes are made available to end users.
This mode is protected, but accessible.
12.2 Memory Map and Registers
This section provides a detailed description of all flash memory registers.
12.2.1 Module Memory Map
The flash memory map is shown below. The addresses are given as an offset to the flash memory base
address.
There are no program-visible registers that physically reside in the flash. The flash controller contains the
registers to control and configure the flash (see Table 12-3). Only reference these registers with 32-bit
accesses.
12-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor