PXR40RM Datasheet, PDF (423/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

DEAR
Vector
Core (e200z7) Overview
Table 13-24. System Call Interrupt—Register Settings (continued)
Unchanged
IVPR_0:15 || IVOR8_16:27 || 4b0000
13.9.10 Auxiliary Processor Unavailable Interrupt (IVOR9)
The PXR40 does not utilize this interrupt.
13.9.11 Decrementer Interrupt (IVOR10)
A Decrementer interrupt occurs when no higher priority exception exists, a Decrementer exception
condition exists (TSR_DIS=1), and the interrupt is enabled (both TCR_DIE and MSR_EE=1).
The Timer Status Register (TSR) holds the Decrementer interrupt bit set by the Timer facility when an
exception is detected. Software must clear this bit in the interrupt handler to avoid repeated Decrementer
interrupts.
Table below lists register settings when a Decrementer interrupt is taken.
Table 13-25. Decrementer Interrupt—Register Settings
Register
Setting Description
SRR0
SRR1
MSR
ESR
MCSR
DEAR
Vector
Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
Set to the contents of the MSR at the time of the interrupt
UCLE 0
SPE 0
WE 0
CE —
EE 0
PR 0
FP 0
ME —
FE0 0
DE —
FE1 0
IS 0
DS 0
PMM 0
RI —
Unchanged
Unchanged
Unchanged
IVPR_0:15 || IVOR10_16:27 || 4b0000
13.9.12 Fixed-Interval Timer Interrupt (IVOR11)
The triggering of the exception is caused by selected bits in the Time Base register changing from 0 to 1.
A Fixed-Interval Timer interrupt occurs when no higher priority exception exists, a FIT exception exists
(TSR_FIS=1), and the interrupt is enabled (both TCR_FIE and MSR_EE=1).
The Timer Status Register (TSR) holds the FIT interrupt bit set by the Timer facility when an exception is
detected. Software must clear this bit in the interrupt handler to avoid repeated FIT interrupts.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-35