PXR40RM Datasheet, PDF (270/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
7.4.2 Reset Control
The reset controller logic is located in the SIU. Refer to Section 7.2.1.1, Reset Input (RESET), and
Section 7.2.1.2, Reset Output (RSTOUT), for details on the reset operations.
7.4.2.1 Reset Boot Configuration
The BOOTCFG[0:1] pins are latched CFG_SAMPLE_CLKS prior to the negation of the RSTOUT pin,
except in the case of a Software External Reset. The values latched are placed in the BOOTCFG field of
the Reset Status Register. Refer to Section 4.7.1.1, RCHW Overview, for details on the RCHW.
7.4.2.2 RESET Pin Glitch Detect
The reset controller provides a glitch detect feature on the RESET pin. If the reset controller detects that
the RESET pin is asserted for more than two clock cycles, the event is latched. After the latch is set, if the
RESET pin is negated before 10 clock cycles is reached, the reset controller sets the RGF bit without
affecting any of the other bits in the reset status register (SIU_RSR). The latch is cleared when the RGF
bit is set or a valid reset is recognized. The RGF bit remains set until cleared by a software or the RESET
signal asserts for 10 clock cycles. The reset controller does not respond to assertions of the RESET pin if
a reset cycle is already being processed.
7.4.3 External Interrupts
There are 16 external interrupt inputs IRQ[0]–IRQ[15] to the SIU. The IRQ inputs can be configured for
rising-edge events, falling-edge events, or both.
External interrupt requests are triggered by rising- and/or falling-edge events that are enabled by setting a
bit in:
• IRQ rising-edge event enable register (SIU_IREER)
• IRQ falling-edge event enable register (SIU_IFEER)
If the bit is set in both registers, both rising- and falling-edge events trigger an interrupt request. Each IRQ
has a counter that tracks the number of system clock cycles that occur between the rising- and falling-edge
events. An IRQ counter exists for each IRQ rising- or falling-edge event enable bit.
The digital filter length field in the IRQ digital filter register (SIU_IDFR) specifies the minimum number
of system clocks that the IRQ signal must hold a logic value to qualify the edge-triggered event as a valid
state change. When the number of system clocks in the IRQ counter equals the value in the digital filter
length field, the IRQ state latches and the IRQ counter is cleared.
If the previous filtered state of the IRQ does not match the current state, and the rising- or falling-edge
event is enabled, the IRQ flag bit is set to 1. For example, the IRQ flag bit is set if a rising-edge event
occurs under the following conditions:
• Previous filtered IRQ state was a logic 0
• Current latched IRQ state is a logic 1
• Rising-edge event is enabled for the IRQ
7-88
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor