PXR40RM Datasheet, PDF (912/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
The Master places its second data bit on the SOUT line one system clock after odd numbered SCK edge.
The point where the Master samples the Slave SOUT is selected by writing to the SMPL_PT field in the
DSPI_MCR. The SMPL_PT field description in Table 25-5 lists the number of system clock cycles
between the active edge of SCK and the Master Sample point. The Master sample point can be delayed by
one or two system clock cycles.
Figure 25-31 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is
illustrated. The delayed Master sample points are indicated with a lighter shaded arrow.
System
Clock
12
3 45 6
SCK
Slave
Sample
Master
Sample
Slave
SOUT
Master
SOUT
PCS
t_CSC
Sys Sys
Clk Clk
t_ASC
t_ASC = After SCK delay
t_{CSC = PCS to SCK delay}
Figure 25-31. DSPI Modified Transfer Format (MTFE=1, CPHA=0, f_sck = f_periph/4)
25.4.7.4 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1)
Figure 25-32 shows the Modified Transfer Format for CPHA = 1. Only the condition where CPOL = 0 is
described. At the start of a transfer the DSPI asserts the PCS signal to the slave device. After the PCS to
SCK delay has elapsed the master and the slave put data on their SOUT pins at the first edge of SCK. The
Slave samples the Master SOUT signal on the even numbered edges of SCK. The Master samples the
Slave SOUT signal on the odd numbered SCK edges starting with the third SCK edge. The Slave samples
the last bit on the last edge of the SCK. The Master samples the last Slave SOUT bit one half SCK cycle
after the last edge of SCK. No clock edge will be visible on the Master SCK pin during the sampling of
the last bit. The SCK to PCS delay must be greater or equal to half of the SCK period.
25-52
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor