PXR40RM Datasheet, PDF (1211/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.2.10.1 ETPUCxCR - eTPU Channel x Configuration Register
ETPUCxCR gathers configurations set individually per channel.
Channel_Register_Base + 0x0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CIE DTRE CPR
0
0 ETPD ETCS 0
0
0
CFS
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R ODIS OPO 0
0
0
CPBA
W
L
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 29-23. ETPUCxCR Register
NOTE
The fields ETCS, CFS and CPBA must only be changed while the channel
is disabled (field CPR=00).
CIE — Channel Interrupt Enable
(this bit is mirrored from ETPUCIER - see Section 29.2.9.5, ETPUCIER - eTPU Channel Interrupt
Enable Register)
1 = Enable interrupt for this channel.
0 = Disable interrupt for this channel.
See the eTPU Reference Manual for details.
DTRE — Channel Data Transfer Request Enable
(this bit is mirrored from ETPUCDTRER - see Section 29.2.9.6, ETPUCDTRER - eTPU Channel Data
Transfer Request Enable Register)
1 = Enable data transfer request for this channel.
0 = Disable data transfer request for this channel.
See the eTPU Reference Manual for details.
CPR[0:1] — Channel Priority
This field defines the priority level for the channel, used by the Hardware Scheduler (See
Section 29.3.3, Scheduler).
Table 29-15. Priority level Bits
CPR
00
01
10
Priority
Disabled
Low
Middle
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-43