PXR40RM Datasheet, PDF (170/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Table 6-8. Output Divide Ratios
ERFD
.
.
.
11_1100
11_1101
11_1110
11_1111
Output Divide Ratio (ERFD+1)
.
.
.
Invalid
Divide-by-62
Invalid
Divide-by-64
6.3.2.4 FMPLL Synthesizer FM Control Register (SYNFMCR)
The synthesizer FM control register (SYNFMCR) contains bits for enabling and configuring PLL
frequency modulation.
Offset: FMPLL_BASE_ADDR + 0x0020
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
FMD
W
AC_E
N
FMDAC_CTL
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-6. FMPLL Synthesizer FM Control Register (SYNFMCR)
Table 6-9. ESYNFMCR Bit Field Descriptions
Field
0
1
FMDAC_EN
2–10
Description
Reserved
Frequency Modulation Register Enable. When this bit is set, the FMDAC_CTL field is enabled and the FM
depth can be controlled directly by the value in FMDAC_CTL. The ESYNCR2[EDEPTH] field must also be
set to a non-zero value to enable FM.
0 FMDAC_CTL disabled.
1 FMDAC_CTL enabled. DAC is controlled by the value in FMDAC_CTL.
Reserved
6-12
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor