PXR40RM Datasheet, PDF (585/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Chapter 22 FlexRay Communication Controller (FLEXRAY)
22.1 Introduction
22.1.1 Reference
The following documents are referenced.
• FlexRay Communications System Protocol Specification, Version 2.1 Rev A
• FlexRay Communications System Electrical Physical Layer Specification, Version 2.1 Rev A
22.1.2 Glossary
This section provides a list of terms used in the description of the controller.
Table 22-1. List of Terms
Term
BCU
BMIF
CC
CDC
CHI
Cycle length in T
EBI
FlexRay Memory
System Memory
System Bus
FSS
HIF
Host
LUT
MB
MBIDX
MBNum
MCU
T
MT
Definition
Buffer Control Unit. Handles message buffer access.
Bus Master Interface. Provides master access to FlexRay Memory block.
Communication Controller
Clock Domain Crosser
Controller Host Interface
The actual length of a cycle in T for the ideal controller (+/- 0 ppm)
External Bus Interface
Memory Window to store message buffer payload, header, status, and synchronization frame
related tables.
Memory that is contains the FlexRay Memory
Bus that connects the controller and System Memory
Frame Start Sequence
Host Interface. Provides host access to controller.
The FlexRay CC host MCU
Look Up Table. Stores message buffer header index value.
Message Buffer
Message Buffer Index: the position of a header field entry within the header area. If the header area
is accessed as an array, this is the same as the array index of the entry.
Message Buffer Number: Position of message buffer configuration registers within the register map.
For example, Message Buffer Number 5 corresponds to the MBCCS5 register.
Microcontroller Unit
Microtick
Macrotick
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-1