PXR40RM Datasheet, PDF (940/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Table 26-8. eSCI_CR2 Field Descriptions (continued)
Field
FEIE
PFIE
Description
Frame Error Interrupt Enable. This bit controls the eSCI_IFSR1[FE] interrupt request generation.
0 FE interrupt request generation disabled.
1 FE interrupt request generation enabled.
Parity Error Interrupt Enable. This bit controls the eSCI_IFSR1[PF] interrupt request generation.
0 PF interrupt request generation disabled.
1 PF interrupt request generation enabled.
26.3.2.4 SCI Data Register (ESCI_DR)
eSCI_BASE + 0x0006
Write: Anytime
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R RN
ERR 0
TN
W
RD[11:8]
RD[7]
TD[7]
RD[6:0]
TD[6:0]
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-5. SCI Data Register (ESCI_DR)
This register is used to provide transmit data and retrieve received data in SCI mode. In LIN mode any
write access to this register is ignored and any read access returns all 0. In case of data transmission this
register is used to provide a part of the transmit data. In case of data reception this register provides a part
of the received data and related error information.If the application writes to the lower byte of this register
(ESCI_DR[8:15]), the internal commit flag iCMT, which is not visible to the application, is set to indicate
that the register has been updated and ready to transmit new data.
If the application reads from the lower byte of this register (ESCI_DR[8:15]), a signal is send to the
internal receiver unit to indicate that the register was read and is ready to receive new data. The read access
will not change the content of any register.
Table 26-9. ESCI_DR Field Descriptions
Field
RN
TN
ERR
Description
Received Most Significant Bit. The semantic of this bit depends on the frame format selected by eSCI_CR3[M2],
eSCI_CR1[M], and eSCI_CR1[PE].
[M2=0,M=1,PE=0]: value of received data bit 8 or address bit.
[M2=0,M=1,PE=1]: value of received parity bit if eSCI_CR2[PMSK]=0, 0 otherwise.
[M2=1,M=0,PE=1]: value of received parity bit if eSCI_CR2[PMSK]=0, 0 otherwise.
[M2=1,M=1,PE=1]: value of received parity bit if eSCI_CR2[PMSK]=0, 0 otherwise.
It is 0 for all other frame formats.
Transmit Most Significant Bit. The semantic of this bit depends on the frame format selected by eSCI_CR3[M2],
eSCI_CR1[M], and eSCI_CR1[PE].
[M2=0,M=1,PE=0]: value to be transmitted as data bit 8 or address bit.
It is not used for all other frame formats.
Receive Error Bit. This bit indicates the occurrence of the errors selected by the Control Register 3 (eSCI_CR3)
during the reception of the frame presented in SCI Data Register (ESCI_DR). In case of an overrun error for
subsequent frames this bit is set too.
0 None of the selected errors occured.
1 At least one of the selected errors occured.
26-12
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor