PXR40RM Datasheet, PDF (1338/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
The NPC implements a Nexus controller state machine that transitions based on the state of the IEEE
1149.1-2001 state machine shown in Figure 31-5. The Nexus controller state machine is defined by the
IEEE-ISTO 5001-2011. It is shown in Figure 31-10.
The instructions implemented by the NPC TAP controller are listed in Table 31-13. The value of the
NEXUS-ENABLE instruction is 0b0000. Each unimplemented instruction acts like the BYPASS
instruction. The size of the NPC instruction register is 4-bits.
Table 31-13. Implemented Instructions
Instruction Name
NEXUS-ENABLE
BYPASS
Private/Public
Public
Private
Opcode
0x0
0xF
Description
Activate Nexus controller state machine to read and
write NPC registers.
NPC BYPASS instruction. Also the value loaded into
the NPC IR upon exit of reset.
Data is shifted between TDI and TDO starting with the least significant bit as illustrated in Figure 31-8.
This applies for the instruction register and all Nexus tool-mapped registers.
msb
lsb
TDI
Selected register
TDO
Figure 31-8. Shifting Data Into a Register
31.7.2.3.1 Enabling the NPC TAP Controller
Assertion of the power-on reset signal or negating JCOMP resets the NPC TAP controller. When not in
power-on reset, the NPC TAP controller is enabled by asserting JCOMP and loading the
ACCESS_AUX_TAP_NPC instruction in the JTAGC. Loading the NEXUS-ENABLE instruction then
grants access to NPC registers.
31-22
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor