PXR40RM Datasheet, PDF (430/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
Table 13-34. Performance Monitor Interrupt—Register Settings (continued)
Register
Setting Description
MSR
ESR
MCSR
DEAR
Vector
UCLE 0
SPE 0
WE 0
CE —
EE 0
PR 0
FP 0
ME —
FE0 0
DE —
Unchanged
Unchanged
Unchanged
IVPR_0:15 || IVOR35_16:27 || 4b0000
FE1 0
IS 0
DS 0
PMM 0
RI —
13.10 Special Features
This section describes the WAIT instruction, VLE save/restore, and performance monitor.
13.10.1 WAIT APU
The wait instruction allows software to shutdown the core and wait for an asynchronous interrupt or debug
interrupt to occur. The instruction can be used to cease processor activity in both user and supervisor
modes. Asynchronous interrupts which will cause the waiting state to be exited if enabled are critical input,
external input, machine check pin, and Non-maskable interrupts (NMI).
Executing a wait instruction ensures that all instructions have completed before the wait instruction
completes, causes processor instruction fetching to cease, and ensures that no subsequent instructions are
initiated until an asynchronous interrupt or a debug interrupt occurs.
Once the wait instruction has completed, the program counter will point to the next sequential instruction.
Wait instruction can be used in conjunction with the SIU_HALT mechanism and SIU_HLTACK registers
to enter a low power state while waiting.
Software must ensure that interrupts responsible for exiting the waiting state are enabled before executing
a wait instruction.
13-42
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor