PXR40RM Datasheet, PDF (1373/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Nexus Development Interface (NDI)
31.14.8.1 Single Write Access
1. Initialize the read/write access address register (RWA) through the access method outlined in
Section 31.11.1, NZ7C3 Register Access via JTAG / OnCE, using the Nexus register index of 0x9
(see Table 31-23). Configure the write address to 0xnnnnnnnn (write address).
2. Initialize the read/write access control/status register (RWCS) through the access method outlined
in Section 31.11.1, NZ7C3 Register Access via JTAG / OnCE, using the Nexus Register Index of
0x7 (see Table 31-23). Configure the bits as follows:
– Access Control RWCS[AC]  0b1 (to indicate start access)
– Map Select RWCS[MAP]  0b000 (primary memory map)
– Access Priority RWCS[PR]  0b00 (lowest priority)
– Read/Write RWCS[RW]  0b1 (write access)
– Word Size RWCS[SZ]  0b0xx (32-bit, 16-bit, 8-bit)
– Access Count RWCS[CNT]  0x0000 or 0x0001 (single access)
NOTE
Access count RWCS[CNT] of 0x0000 or 0x0001 performs a single access.
3. Initialize the read/write access data register (RWD) through the access method outlined in
Section 31.11.1, NZ7C3 Register Access via JTAG / OnCE, using the Nexus register index of 0xA
(see Table 31-23). Configure the write data to 0xnnnnnnnn (write data).
4. The NZ7C3 module then arbitrates for the system bus and transfer the data value from the data
buffer RWD register to the memory mapped address in the read/write access address register
(RWA). When the access has completed without error (ERR=1’b0), NZ7C3 asserts the RDY pin
and clears the DV bit in the RWCS register. This indicates that the device is ready for the next
access.
NOTE
Only the RDY pin as well as the DV and ERR bits within the RWCS provide
read/write access status to the external development tool.
31.14.8.2 Block Write Access (Non-Burst Mode)
1. For a non-burst block write access, follow Steps 1, 2, and 3 outlined in Section 31.14.8.1, Single
Write Access to initialize the registers, but using a value greater than one (0x1) for the
RWCS[CNT] field.
2. The NZ7C3 module then arbitrates for the system bus and transfer the first data value from the
RWD register to the memory mapped address in the read/write access address register (RWA).
When the transfer has completed without error (ERR = 0), the address from the RWA register is
incremented to the next word size (specified in the SZ field) and the number from the CNT field is
decremented. Nexus then asserts the RDY pin. This indicates it is ready for the next access.
3. Repeat step 3 in Section 31.14.8.1, Single Write Access, until the internal CNT value is zero (0).
When this occurs, the DV bit within the RWCS is cleared to indicate the end of the block write
access.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31-57