PXR40RM Datasheet, PDF (769/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
23.4.1.1.6 Double Action Output Compare (DAOC) Mode
In the DAOC mode the leading and trailing edges of the variable pulse-width output are generated by
matches occurring on comparators A and B, respectively.
When the DAOC mode is entered (coming out of GPIO mode), both comparators are disabled and the
output flip-flop is set to the complement of the EDPOL bit in the EMIOS_CCR[n] register
Data written to A2 and B2 are transferred to A1 and B1, respectively, on the next system clock cycle if the
OU[n] bit in EMIOS_OUDR register is cleared (see Figure 23-24). The transfer is blocked if the OU[n]
bit is set. Comparator A is enabled only after the transfer to A1 register occurs, and is disabled on the next
A match. Comparator B is enabled only after the transfer to B1 register occurs, and is disabled on the next
B match. Comparators A and B are enabled and disabled independently.
The output flip-flop is set to the value of EDPOL when a match occurs on comparator A and to the
complement of EDPOL when a match occurs on comparator B.
MODE[6] controls if the FLAG bit is set on both matches or on the second match only (see Table 23-9 for
details). FLAG bit assertion depends on comparator enabling.
If subsequent enabled output compares occur on registers A1 and B1, pulses continue to be generated,
regardless of the state of the FLAG bit.
At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a comparison event in comparator A or B, respectively. The FLAG bit is not affected by
these forced operations.
NOTE
If both A1 and B1 registers are loaded with the same value, the B match
prevails concerning the output pin state. The output flip-flop is set to the
complement of EDPOL, the FLAG bit is set, and both comparators are
disabled.
Figure 23-22 and Figure 23-23 show how the unified channel can be used to generate a single output pulse
with FLAG bit being set on the second match or on both matches, respectively.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-29