PXR40RM Datasheet, PDF (939/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Table 26-8. eSCI_CR2 Field Descriptions (continued)
Field
BSTP
BERRIE
RXDMA
TXDMA
BRCL
TXDIR
BESM
BESTP
RXPOL
PMSK
ORIE
NFIE
Description
DMA Stop on Bit Error or Physical Bus Error. This bit controls the transmit DMA requests generation in case of
bit errors or physical bus errors. Bit errors are indicated by the BERR flag in the Interrupt Flag and Status Register
1 (eSCI_IFSR1) and physical bus errors are indicated by the PBERR flag in the Interrupt Flag and Status
Register 2 (eSCI_IFSR2).
0 Transmit DMA requests generated regardless of bit errors or physical bus errors.
1 Transmit DMA requests are not generated if eSCI_IFSR1[BERR] flag or eSCI_IFSR2[PBERR] flags are set.
Note: This bit is used in LIN mode only.
Bit Error Interrupt Enable. This bit controls the BERR interrupt request generation.
0 BERR interrupt request generation disabled.
1 BERR interrupt request generation enabled.
Receive DMA Control. This bit enables the receive DMA feature.
0 Receive DMA disabled.
1 Receive DMA enabled.
Transmit DMA Control. This bit enables the transmit DMA feature.
0 Transmit DMA disabled.
1 Transmit DMA enabled.
Break Character Length. This bit is used to define the length of the break character to be transmitted.
The settings are specified in Section 26.4.2.2, Break Character Formats.
TXD pin output enable. This bit determines whether the TXD pin is used as an output.
0 TXD pin is not used as output.
1 TXD pin is used as output.
Note: This bit is used in Single Wire Mode only.
Fast Bit Error Detection Sample Mode. This bit defines the sample point for the Fast Bit Error Detection Mode.
0 Sample point is RS9.
1 Sample point is RS13.
Note: This bit is used in LIN mode only.
Transmit Stop on Bit Error. If this control bit is set, the eSCI stops driving the LIN bus immediately when a Bit
Error has been detected, i.e. eSCI_IFSR1[BERR]=1. Additionally, the eSCI will not start a new byte transmission
as long the BERR interrupt flag is set.
0 Transmission is not stopped on bit error.
1 Transmission is stopped on bit error.
Note: This bit is used in LIN mode only.
RXD Pin polarity. This bit controls the polarity of the RXD pin. See Section 26.4.2.1.1, Inverted Data Frame
Formats
0 Normal Polarity.
1 Inverted Polarity.
Parity Bit Masking. This bit defines whether the received parity bit is presented in the related bit position in the
SCI Data Register (ESCI_DR).
0 The received parity bit is presented in the bit position related to the parity bit.
1 The value 0 is presented in the bit position related to the parity bit.
Overrun Interrupt Enable. This bit controls the eSCI_IFSR1[OR] interrupt request generation.
0 OR interrupt request generation disabled.
1 OR interrupt request generation enabled.
Noise Interrupt Enable. This bit controls the eSCI_IFSR1[NF] interrupt request generation.
0 NF interrupt request generation disabled.
1 NF interrupt request generation enabled.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
26-11