PXR40RM Datasheet, PDF (1068/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
NOTE
An asserted EOQFx only implies that EQADC has finished transferring a
command with an asserted EOQ bit from CFIFOx. It does not imply that
result data for the current command and for all previously transferred
commands has been returned to the appropriate RFIFO.
27.7.4.7.3 Pause Status
In edge trigger mode, when the EQADC completes the transfer of a CFIFO entry with an asserted Pause
bit, the EQADC will stop future command transfers from the CFIFO and set the corresponding Pause Flag
(PF) in Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR). Refer to
Section 27.7.2.2, Message Format in EQADC, for information on command message formats. The
EQADC ignores the Pause bit in command messages in any software and external level trigger mode. The
EQADC sets the PF flag upon detection of an asserted Pause bit only in single or continuous-scan edge
trigger mode. When the PF flag is set for a CFIFO in single-scan edge trigger mode, the SSS bit will not
be cleared in Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR).
In level trigger mode, the definition of the PF flag has been redefined. In level trigger mode, when CFIFOx
is in TRIGGERED status, PFx is set when CFIFO status changes from TRIGGERED due to detection of
a closed gate. The pause flag interrupt routine can be used to verify if the a complete scan of the CQueue
was performed. If a closed gate is detected while no command transfers are taking place, it will have
immediate effect on the CFIFO status.
When PIE in Section 27.6.2.5, EQADC CFIFO Control Registers (EQADC_CFCR), and PF are asserted,
the EQADC will generate a Pause interrupt request.
NOTE
In edge trigger mode, an asserted PFx only implies that the EQADC finished
transferring a command with an asserted PAUSE bit from CFIFOx. It does
not imply that result data for the current command and for all previously
transferred commands has been returned to the appropriate RFIFO.
NOTE
In software or level trigger mode, when the EQADC completes the transfer
of an entry from CFIFOx with an asserted Pause bit, PFx will not be set and
command transfers will continues without pausing.
27.7.4.7.4 Trigger Overrun Status
NOTEWhen a CFIFO is configured for edge- or level-trigger mode and is in TRIGGERED state, an
additional trigger occurring for the same CFIFO results in a trigger overrun. The trigger overrun bit for the
corresponding CFIFO will be set (TORFx = 1) in Section 27.6.2.7, EQADC FIFO and Interrupt Status
Registers (EQADC_FISR). When TORIE in Section 27.6.2.5, EQADC CFIFO Control Registers
(EQADC_CFCR), and TORF are asserted, the EQADC generates a trigger overrun interrupt request.
For CFIFOs configured for level-trigger mode, a trigger overrun does not
occur.
27-86
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor