PXR40RM Datasheet, PDF (768/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
EMIOS_CBDR[n] register. Reading EMIOS_CBDR[n] register forces A1 content to be transferred to B1
and re-enables transfers from B2 to B1, to take effect at the next edge capture.
The input pulse period is calculated by subtracting the value in B1 from A2.
Figure 23-20 shows how the unified channel can be used for input period measurement.
EDPOL = 1
Input signal¹
selected counter bus
0x000500
A
0x001000
0x001100
A
0x001250
0x001525
A
0x0016A0
FLAG pin register
A2(captured) value²
B2 (captured) value
A1 value
B1 value³
Notes: 1. After input filter
2. EMIOSA[n] = A2
3. EMIOSB[n] = B1
$0xxxxxxx
$0xxxxxxx
$0xxxxxxx
$0xxxxxxx
0x001000
0x001000
0x001250
0x001250
0x001000
0x001000
Figure 23-20. IPM Example
0x0016A0
0x0016A0
0x001250
0x001250
Figure 23-21 shows the A1 and B1 register updates when EMIOS_CADR[n] and EMIOS_CBDR[n] read
operations are performed. When a EMIOS_CADR[n] read occurs, the contents of A1 are transferred to
B1, thus providing coherent data in the A2 and B1 registers. Transfers from B2 to B1 are then blocked until
EMIOS_CBDR[n] is read. After EMIOS_CBDR[n] is read, the contents of register A1 are transferred to
register B1 and the transfers from B2 to B1 are re-enabled to occur at the transfer edges, which is the
leading edge in the Figure 23-21 example.
EDPOL = 1
A
Read EMIOS_CADR[n]
A
Read EMIOS_CBDR[n]
A
Input Signal¹
Selected
Counter Bus
0x000500
0x001000
0x001100
0x001250
0x001525
0x0016A0
FLAG Set Event
A2 (Captured) Value^{2 0xxxxxxx}
B2 (Captured) Value 0xxxxxxx
0x001100
0x001000
0x001250
0x001250
0x001525
0x0016A0
A1 Value 0xxxxxxx
0x001000
0x001250
B1 Value^{3 0xxxxxxx}
0x001000
0x001000
0x001250
Notes:
1. After input filter
2. EMIOS_CADR[n] = A2
3. EMIOS_CBDR[n] = B1
Figure 23-21. A1 and B1 Updates at EMIOS_CADR[n] and EMIOS_CBDR[n] Reads
23-28
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor