PXR40RM Datasheet, PDF (1296/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
D_CLKOUT
D_ADD[9:30]
D_ADD[29:31] = ‘000’
D_RD_WR
D_TS
D_BDIP
Expects more data
D_ADD_DAT[0:31]
D_TA
CS[n]
D_ADD_DAT is valid
Wait state
Wait state
Wait state
Wait state
D_OE
Figure 30-25. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP=0
When using TBDIP=1, the D_BDIP behavior changes to toggle between every beat when BSCY is a
non-zero value. Figure 30-26 shows an example of the TBDIP=1 timing for the same 4-beat burst shown
in Figure 30-25.
D_CLKOUT
D_ADD[9:30]
D_ADD[29:31] = ‘000’
D_RD_WR
D_TS
D_BDIP
Expects more data
D_ADD_DAT[0:31]
D_TA
CS[n]
D_ADD_DAT is valid
Wait state
Wait state
Wait state
Wait state
D_OE
Figure 30-26. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP=1
30-34
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor