PXR40RM Datasheet, PDF (1286/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
D_CLKOUT
D_ADD[9:30]
D_RD_WR
D_BDIP
D_TS
D_ADD_DAT[0:31]
D_TA
CS[n]
Wait state
D_ADD_DAT is valid
D_OE
Figure 30-11. Single Beat 32-bit Read Cycle, CS Access, One Wait State
D_CLKOUT
D_ADD[9:30]
*
D_RD_WR
D_BDIP
D_TS
D_ADD_DAT[0:31]
D_TA (Input)
CS[n]
D_ADD_DAT is valid
D_OE
* The EBI drives address and control signals an extra cycle because it uses a latched
version of the external D_TA (1 cycle delayed) to terminate the cycle.
Figure 30-12. Single Beat 32-bit Read Cycle, Non-CS Access, Zero Wait States
30.4.2.4.2 Single Beat Write Flow
The handshakes for a single beat write cycle are illustrated in the following flow and timing diagrams.
30-24
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor