PXR40RM Datasheet, PDF (766/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
23.4.1.1.4 Input Pulse-Width Measurement (IPWM) Mode
The IPWM mode (MODE = 000_0100) allows measuring the width of a positive or negative pulse by
capturing the leading edge on register B1 and the trailing edge on register A2. Successive captures are done
on consecutive edges of opposite polarity. The leading edge sensitivity (i.e., pulse polarity) is selected by
the EDPOL bit in the EMIOS_CCR[n] register. Registers EMIOS_CADR[n] and EMIOS_CBDR[n]
return the values in register A2 and B1, respectively.
The capture function of register A2 remains disabled until the first leading edge triggers the first input
capture on register B2. When this leading edge is detected, the count value of the selected time base is
latched into register B2; the FLAG bit is not set. When the trailing edge is detected, the count value of the
selected time base is latched into register A2. At the same time, the FLAG bit is set and the content of
register B2 is transferred to register B1 and to register A1.
If subsequent input capture events occur while the corresponding FLAG bit is set, registers A2, B1, and
A1 are updated with the latest captured values and the FLAG remains set. Registers EMIOS_CADR[n]
and EMIOS_CBDR[n] return the value in registers A2 and B1, respectively.
In order to guarantee coherent access, reading EMIOS_CADR[n] forces B1 to be updated with the content
of register A1. At the same time, transfers between B2 and B1 are disabled until the next read of
EMIOS_CBDR[n] register. Reading EMIOS_CBDR[n] register forces B1 be updated with A1 register
content and re-enables transfers from B2 to B1, to take effect at the next trailing edge capture. Transfers
from B2 to A1 are not blocked at any time.
The input pulse width is calculated by subtracting the value in B1 from A2.
Figure 23-18 shows how the unified channel can be used for input pulse-width measurement.
EDPOL = 1
B
A
B
A
B
Input Signal¹
Selected
Counter Bus
FLAG Set Event
A2 (Captured) Value²
B2 (Captured) Value
A1 Value³
B1 Value³
0x000500
0xxxxxxx
0xxxxxxx
0xxxxxxx
0xxxxxxx
0x001000
0x001000
0x001100
0x001100
0x001000
0x001000
0x001250
0x001250
0x001525
0x001525
0x001250
0x001250
0x0016A0
0x0016A0
Notes: 1. After input filter
2. EMIOS_CADR[n] = A2
3. EMIOS_CBDR[n] = B1
Figure 23-18. IPWM Example
Figure 23-19 shows the A1 and B1 updates when EMIOS_CADR[n] and EMIOS_CBDR[n] register reads
occur. The A1 register has always coherent data related to the A2 register. When a EMIOS_CADR[n] read
is performed, the B1 register is loaded with the A1 register content. This guarantees that the data in register
B1 always has the coherent data related to the last EMIOS_CADR[n] read. The B1 register updates remain
23-26
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor