PXR40RM Datasheet, PDF (887/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 25-20. DSPI_DSICR Field Descriptions (continued)
Field
Description
14
TRRE
15
CID
16
DCONT
17–19
DSICTAS
Trigger Reception Enable. The TRRE bit enables the DSPI to initiate a transfer when an external
trigger signal is received. The bit is only valid in DSI configuration. See Section 25.4.4.5, DSI Transfer
Initiation Control, for more information. When TSBC bit is set, TRRE bit is used for both DSICR and
DSICR1 registers.
0 Trigger signal reception disabled
1 Trigger signal reception enabled
Change In Data Transfer Enable. The CID bit enables a change in serialization data to initiate a
transfer. The bit is used in Master Mode in DSI and CSI configurations to control when to initiate
transfers. When the CID bit is set, serialization is initiated when the current DSI data differs from the
previous DSI data shifted out. The DSPI_COMPR register is compared with the DSPI_SDR or
DSPI_ASDR register to detect a change in data. Refer to Section 25.4.4.5, DSI Transfer Initiation
Control, for more information. When TSBC bit is set, CID bit is used for both DSICR and DSICR1
registers.
DSI Continuous Peripheral Chip Select Enable. The DCONT bit enables the PCS signals to remain
asserted between transfers. The DCONT bit only affects the PCS signals in DSI Master Mode. See
Section 25.4.7.5, Continuous Selection Format, for details. When TSBC bit is set, DCONT bit is used
for both DSICR and DSICR1 registers.
0 Return Peripheral Chip Select signals to their inactive state after transfer is complete
1 Keep Peripheral Chip Select signals asserted after transfer is complete
DSI Clock and Transfer Attributes Select. The DSICTAS field selects which of the DSPI_CTAR register
is used to provide transfer attributes in DSI configuration. The DSICTAS field is used in DSI Master
Mode. In DSI Slave Mode, the DSPI_CTAR1 is always selected. The table below shows how the
DSICTAS values map to the DSPI_CTAR registers. When TSB configuration is selected the DSICTAS
bits control all 32 bits.
DSICTAS
000
001
010
011
DSI Clock and Transfer
Attributes Controlled by
DSPI_CTAR0
DSPI_CTAR1
DSPI_CTAR2
DSPI_CTAR3
DSICTAS
100
101
110
111
DSI Clock and Transfer
Attributes Controlled by
DSPI_CTAR4
DSPI_CTAR5
DSPI_CTAR6
DSPI_CTAR7
20–25
26–31
DPCSx
Reserved, should be cleared.
DSI Peripheral Chip Select 0–7. The DPCS bits select which of the PCS signals to assert during a
DSI transfer. The DPCS bits only control the assertions of the PCS signals in DSI Master Mode.
0 Negate PCS[x]
1 Assert PCS[x]
25.3.2.11 DSPI DSI Serialization Data Register (DSPI_SDR)
The DSPI_SDR contains the signal states of the Parallel Input signals. The pin states of the Parallel Input
signals are latched into the DSPI_SDR on the rising edge of every system clock. The DSPI_SDR is
read-only. When the TXSS bit in the DSPI_DSICR is negated, the data in the DSPI_SDR is the source of
the serialized data.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-27