PXR40RM Datasheet, PDF (343/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Interrupts and Interrupt Controller (INTC)
After generating a software configurable interrupt request, the higher priority ISR completes. The lower
priority ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed after
the completion of the lower priority ISR.
10.5.7.2 Scheduling an ISR on Another Processor
Since the SETn bits in the INTC_SSCIRn are memory mapped, processors in multiple processor systems
can schedule ISRs on the other processors. One application is that one processor simply wants to command
another processor to perform a piece of work, and the initiating processor does not need to use the results
of that work. If the initiating processor is concerned that processor executing the software configurable
ISR has not completed the work before asking it to again execute that ISR, it can check if the
corresponding CLRn bit in INTC_SSCIRn is asserted before again writing a 1 to the SETn bit.
Another application is the sharing of a block of data. For example, a first processor has completed
accessing a block of data and wants a second processor to then access it. Furthermore, after the second
processor has completed accessing the block of data, the first processor again wants to access it. The
accesses to the block of data must be done coherently. The procedure is that the first processor writes a 1
to a SETn bit on the second processor. The second processor, after accessing the block of data, clears the
corresponding CLRn bit and then writes 1 to a SETn bit on the first processor, informing it that it now can
access the block of data.
10.5.8 Lowering Priority Within an ISR
In implementations without the software-configurable interrupt requests in the INTC software set/clear
interrupt registers (INTC_SSCIR0–INTC_SSCIR7), a way — besides scheduling a task through an RTOS
— to prevent preemptive scheduling inefficiencies with an ISR whose work spans multiple priorities (as
described in Section 10.5.7.1, Scheduling a Lower Priority Portion of an ISR) is to lower the current
priority. However, the INTC has a LIFO whose depth is determined by the number of priorities.
NOTE
Lowering the PRI value in INTC current priority register (INTC_CPR)
within an ISR to below the ISR’s corresponding PRI value in INTC priority
select registers (INTC_PSR0–INTC_PSR479) allows more preemptions
than the depth of the LIFO can support.
Therefore, through its use of the LIFO the INTC does not support lowering the current priority within an
ISR as a way to avoid preemptive scheduling inefficiencies.
10.5.9 Negating an Interrupt Request Outside of its ISR
10.5.9.1 Negating an Interrupt Request as a Side Effect of an ISR
Some peripherals have flag bits which can be cleared as a side effect of servicing a peripheral interrupt
request. For example, reading a specific register can clear the flag bits, and consequently their
corresponding interrupt requests too. This clearing as a side effect of servicing a peripheral interrupt
request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
10-43