PXR40RM Datasheet, PDF (976/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
System Memory
P[1:0]
ID[5:0]
LEN¹
CSM CSE CRC TD²
TO[11:8]
TO[7:0]
DATA 1
DATA 2
DMA
Controller
TX DMA
channel
RX DMA
channel
eSCI
DATA N
1 _{LEN must be set to N}
2 _{TD must be set to 0}
from LIN Master
Break
Synch Identifier DATA 1
LIN RX frame
from LIN Slave
DATA N
Checksum
Figure 26-41. DMA Controlled LIN RX Frame generation and reception
26.4.6.5 LIN Error Reporting
This section describes error checking and the signaling of detected errors in LIN mode.
26.4.6.5.1 Physical Bus Error Detection
If the receiver input is sampled 0 for at least 31 sample clock cycles after the start of the transmission of a
LIN frame, the physical bus error flag PBERR in the Interrupt Flag and Status Register 2 (eSCI_IFSR2)
will be set.
26.4.6.5.2 Unrequested Activity Detection
If an unrequested byte is received (i.e. a byte which is not part of an RX frame) which is not recognized
as a wakeup or break character, the bit error flag BERR in the Interrupt Flag and Status Register
2 (eSCI_IFSR2) is set. In addition the RXRDY flag will also be set, the LINRX register must be read
before normal operations can proceed.
26.4.6.5.3 Standard Bit Error Detection
The standard bit error detection is performed on each byte field transmission.
During the transmission of the frame header and frame data, the receiver is running and receives the signal
values on the serial bus. After the complete transmission of a byte field, the eSCI compares the data that
was transmitted and the data that was received. If they do not match, the bit error flag BERR in the
Interrupt Flag and Status Register 2 (eSCI_IFSR2) is set.
26.4.6.5.4 Fast Bit Error Detection
Fast Bit Error Detection has been designed to allow flagging of LIN bit errors while they occur, rather than
flagging them after a byte transmission has completed (see Figure 26-42).
26-48
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor